公开(公告)号：WO2015160924A1

公开(公告)日：2015-10-22

申请号：PCT/US2015/025934

申请日：2015-04-15

Applicant: THE BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM

Inventor： CHIU, Yun ,  WU, Bo

IPC: H03F1/08 ,  H03F3/45 ,  H03F3/21

CPC classification number: H03F3/45179 ,  H03F1/086 ,  H03F3/211 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/45237 ,  H03F3/4565 ,  H03F2200/153 ,  H03F2200/408 ,  H03F2203/45116 ,  H03F2203/45222 ,  H03F2203/45236 ,  H03F2203/45418 ,  H03F2203/45481

Abstract: Disclosed are systems implementing an implicit Feed-Forward Compensated (FFC) op-amp, where the main FFC port is realized by the P-side (404) of the CMOS input structure of the 2nd (412) and 3rd (414) stages of the op-amp, while the main signal path is through the N-side (402). The 2nd-stage (412) NMOS input pair is split into two pairs, one is used to route the main path while the other is used for auxiliary FFC. The disclosed implicit FCC op-amp is unconditionally stable with adequate phase lead. According to some embodiments, the disclosed op-amp, which may be a wide-band op-amp, can be used in highly linear applications operative at intermediate frequency (IF), such as signal buffers for high-performance data converters or radio-frequency (RF) modulators and demodulators, continuous-time (CT) filters or sigma-delta data converters.

Abstract translation: 公开了实现隐式前馈补偿（FFC）运算放大器的系统，其中主FFC端口由第二（412）和第（414）级的CMOS输入结构的P侧（404）实现 运算放大器，而主信号路径则通过N侧（402）。 第二级（412）NMOS输入对被分成两对，一个用于路由主路径，另一个用于辅助FFC。 所公开的隐式FCC运算放大器是无条件稳定的，具有足够的相位导联。 根据一些实施例，所公开的可以是宽带运算放大器的运算放大器可以用于在中频（IF）下操作的高度线性的应用中，例如用于高性能数据转换器或无线电设备的信号缓冲器， 频率（RF）调制器和解调器，连续时间（CT）滤波器或Σ-Δ数据转换器。

公开(公告)号：WO1996030999A1

公开(公告)日：1996-10-03

申请号：PCT/US1996004089

申请日：1996-03-26

Applicant: ZERO IMPEDANCE SYSTEMS

Inventor： ZERO IMPEDANCE SYSTEMS ,  FREULER, George, H. ,  COLLIER, Edward, J. ,  MAZI, David ,  MIDDLEBROOK, R., David

IPC: H03F21/00

CPC classification number: H03F3/4521 ,  H03F3/3076 ,  H03F3/3081 ,  H03F3/45224 ,  H03F3/68 ,  H03F2203/45024 ,  H03F2203/45028 ,  H03F2203/45036 ,  H03F2203/45224 ,  H03F2203/45236 ,  H03F2203/45278 ,  H03F2203/45366 ,  H03F2203/45471

Abstract: A coupling circuit composed of an input terminal (22) for receiving an input signal from a source (Vi) and first and second output terminals (26, 28) for supplying an output signal to a load (ZL); a signal processing device (A1) connected between the input terminal (22) and the first output terminal (26) for deriving an output signal from the input signal and for supplying the output signal to a load (ZL) connected between the output terminals (26, 28); a power supply (Vp) having a finite impedance and connected for supplying operating power to the signal processing circuit (A1), a distortion eliminating circuit (A2) connected between the power supply (Vp) and the second output terminal (28) for supplying to the load (ZL) a current which compensates for differences between the waveform of the output signal and the input signal due to the power supply (Vp) impedance, the distortion eliminating device (A2) including at least one active circuit element and having an electric characteristic corresponding substantially to a capacitor with infinite capacitance.

Abstract translation: 一种耦合电路，包括用于从源极（Vi）接收输入信号的输入端子（22）和用于向负载（ZL）提供输出信号的第一和第二输出端子（26,28）; 连接在输入端（22）和第一输出端（26）之间的信号处理装置（A1），用于从输入信号导出输出信号，并将输出信号提供给连接在输出端之间的负载（ZL） 26，28）; 具有有限阻抗并被连接用于向信号处理电路（A1）提供工作电源的电源（Vp）;连接在电源（Vp）和第二输出端子（28）之间的失真消除电路（A2） 负载（ZL）补偿由于电源（Vp）阻抗引起的输出信号的波形与输入信号之间的差异的电流，失真消除装置（A2）包括至少一个有源电路元件，并具有 电特性基本上对应于具有无限电容的电容器。

公开(公告)号：WO2008039503A2

公开(公告)日：2008-04-03

申请号：PCT/US2007020803

申请日：2007-09-26

Applicant: ARAM FARBOD

Inventor： ARAM FARBOD

IPC: H03F1/38 ,  H03F3/16

CPC classification number: H03F1/26 ,  H03F1/42 ,  H03F1/486 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/111 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/36 ,  H03F2200/372 ,  H03F2200/408 ,  H03F2203/45138 ,  H03F2203/45236 ,  H03F2203/45288 ,  H03F2203/45522 ,  H03F2203/45526 ,  H03F2203/45576

Abstract: Aspects provide for the broadband amplification of RF signals. Other aspects provide for the conversion of single ended input to differential output. Various aspects provide for tuning the response to a particular frequency band. Other aspects provide for various transconductance elements. In several aspects, broadband current to voltage converters and voltage to current converters are presented. Some implementations incorporate a buffer circuit, and various implementations incorporate feedback circuits.

Abstract translation: 方面提供了RF信号的宽带放大。 其他方面提供单端输入到差分输出的转换。 各种方面提供了对特定频带的响应的调谐。 其他方面提供了各种跨导元件。 在几个方面，提出了宽带电流到电压转换器和电压到电流转换器。 一些实现包括缓冲电路，并且各种实现包括反馈电路。

公开(公告)号：WO1993019522A1

公开(公告)日：1993-09-30

申请号：PCT/US1993002342

申请日：1993-03-15

Applicant: ZERO IMPEDANCE SYSTEMS, INC.

Inventor： ZERO IMPEDANCE SYSTEMS, INC. ,  FREULER, George, H. ,  COLLIER, Edward, J. ,  MAZI, David, A.

IPC: H03F03/26

CPC classification number: H03F3/4521 ,  H03F3/3076 ,  H03F3/3081 ,  H03F3/45224 ,  H03F3/68 ,  H03F2203/45024 ,  H03F2203/45028 ,  H03F2203/45036 ,  H03F2203/45224 ,  H03F2203/45236 ,  H03F2203/45278 ,  H03F2203/45366 ,  H03F2203/45471

Abstract: A circuit for coupling a signal source (Vi) producing a signal having a given voltage waveform to a load (6) having two ends, the circuit being composed of: a load voltage control unit (A1) connectable between the signal source and one end of the load for producing across the load (6) a voltage corresponding to the signal voltage; and a load current control unit (A2) connectable to the load (6) and operable independently of the signal source (Vi) for producing a current flow through the load (6) sufficient to cause the voltage across the load (6) or the current through the load (5) to have the given waveform.

Abstract translation: 一种用于将产生具有给定电压波形的信号的信号源（Vi）耦合到具有两端的负载（6）的电路，该电路由以下部分组成：负载电压控制单元（A1），可连接在信号源与一端 用于在负载（6）上产生对应于信号电压的电压的负载; 以及负载电流控制单元（A2），其可连接到所述负载（6）并且可独立于所述信号源（Vi）操作，用于产生通过所述负载（6）的电流，所述电流足以使所述负载（6）或 电流通过负载（5）具有给定的波形。

公开(公告)号：WO2013142400A1

公开(公告)日：2013-09-26

申请号：PCT/US2013/032752

申请日：2013-03-18

Applicant: ANALOG DEVICES, INC.

Inventor： HERRERA, Sandro

IPC: H03F3/45

CPC classification number: H03F3/45071 ,  H03F1/3211 ,  H03F3/4508 ,  H03F3/45085 ,  H03F2203/45236 ,  H03F2203/45352 ,  H03F2203/45366

Abstract: A transconductance circuit that improves linearity and output current over a wider range of input voltages than prior designs. The transconductance circuit may include first and second sets of paired differential transistors. In each set, emitters of the paired transistors may be commonly coupled to corresponding nodes of a common impedance, and collectors may be coupled to output terminals of the transconductance circuit. The circuit may further include first and second sets of doublet differential transistor pairs, each doublet pair having transistors of different sizes. Each doublet pair may have current sources coupled between commonly coupled emitters and a source potential. Respective collectors for each doublet pair may be coupled to the output terminals of the transconductance circuit. A pair of voltage followers may be provided to replicate corresponding input voltages across corresponding bases of the differential transistor pairs and the doublet transistor pairs.

Abstract translation: 一种跨导电路，可在比现有设计更宽的输入电压范围内提高线性度和输出电流。 跨导电路可以包括第一组和第二组成对的差分晶体管。 在每组中，成对晶体管的发射极可以共同耦合到公共阻抗的对应节点，并且集电极可以耦合到跨导电路的输出端子。 电路还可以包括第一组和第二组双差分晶体管对，每个双对具有不同尺寸的晶体管。 每个双引线对可以具有耦合在共同耦合的发射极和源极电位之间的电流源。 每个双绞线对的各个集电极可以耦合到跨导电路的输出端子。 可以提供一对电压跟随器来复制跨越差分晶体管对和双晶体管对的对应基极的对应输入电压。

公开(公告)号：WO2008086609A1

公开(公告)日：2008-07-24

申请号：PCT/CA2008/000083

申请日：2008-01-17

Applicant: POWER INTEGRATIONS LIMITED A Cayman Island Company ,  COLBECK, Roger

Inventor： COLBECK, Roger

IPC: H03K5/22 ,  H03F3/45

CPC classification number: H03K5/2481 ,  H03F3/4521 ,  H03F2203/45091 ,  H03F2203/45101 ,  H03F2203/45236

Abstract: A comparator comprises complementary (e.g. NMOS and PMOS) comparator cells (40, 41) having overlapping common mode input voltage ranges which together extend approximately from rail to rail. A digital logic arrangement, including edge detectors (42, 43), gates (44, 45), and a latch (48), is responsive to transitions at the outputs of the comparator cells to set the latch in response to the earliest rising edge and to reset the latch in response to the earliest falling edge. An output of the latch constitutes an output of the comparator. Consequently the comparator is edge-sensitive with a speed optimized for a wide common mode input voltage range. Additional logic gates (46, 47) can provide level-sensitive control of the latch.

Abstract translation: 比较器包括具有重叠的共模输入电压范围的互补（例如NMOS和PMOS）比较器单元（40,41），其共同地从轨到轨延伸。 包括边缘检测器（42,43），门（44,45）和锁存器（48）的数字逻辑装置响应于比较器单元的输出处的转变，以响应于最早的上升沿来设置锁存器 并且响应于最早的下降沿来重置锁存器。 锁存器的输出构成比较器的输出。 因此，比较器是边缘敏感的，具有针对宽共模输入电压范围优化的速度。 附加逻辑门（46,47）可以提供锁存器的电平敏感控制。