公开(公告)号：WO2016183516A1

公开(公告)日：2016-11-17

申请号：PCT/US2016/032531

申请日：2016-05-13

Applicant: RFAXIS, INC.

Inventor： GORBACHOV, Oleksandr ,  ZHANG, Lisette L. ,  MUSIOL, Lothar

IPC: H04B1/04 ,  H03H7/38 ,  H03F3/20 ,  H03F1/56

CPC classification number: H03F3/21 ,  H03F1/34 ,  H03F1/342 ,  H03F1/565 ,  H03F3/191 ,  H03F3/193 ,  H03F3/195 ,  H03F3/45475 ,  H03F2200/144 ,  H03F2200/15 ,  H03F2200/171 ,  H03F2200/225 ,  H03F2200/294 ,  H03F2200/369 ,  H03F2200/372 ,  H03F2200/391 ,  H03F2200/451 ,  H03F2203/45222 ,  H03F2203/45526 ,  H03H11/481

Abstract: A radio frequency (RF) power amplifier circuit includes an input and an output. A power amplifier transistor has a first terminal connected to the input, a second terminal connected to the output, and a third terminal defined by a degeneration inductance. A first capacitor is connected to the third terminal of the power amplifier transistor, along with a negative capacitance circuit connected in series with the first capacitor. The negative capacitance and the first capacitor define a series resonance at a predefined operating frequency band, which shunts the degeneration inductance of the third terminal.

Abstract translation: 射频（RF）功率放大器电路包括输入和输出。 功率放大器晶体管具有连接到输入的第一端子，连接到输出端的第二端子和由退化电感限定的第三端子。 第一电容器连接到功率放大器晶体管的第三端子以及与第一电容器串联连接的负电容电路。 负电容和第一电容器在预定义的工作频带定义串联谐振，其分流第三端子的退化电感。

公开(公告)号：WO2016134604A1

公开(公告)日：2016-09-01

申请号：PCT/CN2015/096818

申请日：2015-12-09

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： LACROIX, Marc-Andre

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  H03F3/193 ,  H03F3/45197 ,  H03F2203/45112 ,  H03F2203/45222 ,  H03F2203/45488 ,  H03F2203/45494 ,  H03G5/14

Abstract: A transadmittance amplifier stage is coupled to a transimpedance amplifier stage to form a continuous time linear equalizer. The transadmittance amplifier stage has first and second gain paths and is configured to input a first signal and output a second signal. The first gain path is configured to provide a DC gain recovery and a first high frequency gain to the first signal. The second gain path is configured to provide a second high frequency gain to the first signal. The second signal is generated by the transadmittance amplifier stage based on the gain recovery of the first signal and the high frequency gains of the first signal. The transimpedance amplifier stage is configured to input the second signal from the transadmittance amplifier stage and convert the second signal to an output voltage signal.

Abstract translation: 跨导放大器级耦合到跨阻放大器级以形成连续时间线性均衡器。 所述互导体放大器级具有第一和第二增益路径，并且被配置为输入第一信号并输出​​第二信号。 第一增益路径被配置为向第一信号提供DC增益恢复和第一高频增益。 第二增益路径被配置为向第一信号提供第二高频增益。 基于第一信号的增益恢复和第一信号的高频增益，由导纳放大器级产生第二信号。 跨阻放大器级被配置为输入来自跨导纳放大器级的第二信号，并将第二信号转换为输出电压信号。

公开(公告)号：WO2011050976A1

公开(公告)日：2011-05-05

申请号：PCT/EP2010/006621

申请日：2010-10-29

Applicant: ST-Ericsson SA ,  TENG, Robert Hwat Hian

Inventor： TENG, Robert Hwat Hian

IPC: H03F3/187 ,  H03F3/45

CPC classification number: H03F3/45475 ,  H03F3/187 ,  H03F3/45179 ,  H03F3/45278 ,  H03F3/45645 ,  H03F3/45928 ,  H03F2200/03 ,  H03F2200/231 ,  H03F2200/234 ,  H03F2200/27 ,  H03F2200/375 ,  H03F2200/396 ,  H03F2200/411 ,  H03F2200/414 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/507 ,  H03F2200/78 ,  H03F2203/45101 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45206 ,  H03F2203/45212 ,  H03F2203/45222 ,  H03F2203/45224 ,  H03F2203/45356 ,  H03F2203/45536 ,  H03F2203/45561 ,  H03F2203/45588 ,  H03F2203/45616 ,  H03F2203/45641 ,  H03F2203/45728

Abstract: An amplifier 100 has an input 108 for receiving a signal to be amplified and an output 110 for outputting an amplified signal. The amplifier 100 comprises a main amplification stage 102, an auxiliary amplification stage 104 and a controller 106. The main amplification stage 102 comprises a main amplification circuit 200 and the auxiliary amplification stage 104 comprises an auxiliary amplification circuit 202. Each of the main amplification circuit 200 and the auxiliary amplification circuit 202 comprises a p-channel metal oxide semiconductor (PMOS) transistor T1, T3 and an n-channel metal oxide semiconductor (NMOS) transistor T2, T4. The PMOS and NMOS transistors T3, T4 of the auxiliary amplification circuit 202 are either identical to the PMOS and NMOS transistors T1, T2 of the main amplification circuit 200 or are scaled down copies of the PMOS and NMOS transistors T1, T2 of the main amplification circuit 200. The auxiliary amplification circuit 202 amplifies the input signal to generate a control signal and the controller 106 controls a function of the amplifier 100 based on the control signal.

Abstract translation: 放大器100具有用于接收要被放大的信号的输入端108和用于输出放大信号的输出端110。 放大器100包括主放大级102，辅助放大级104和控制器106.主放大级102包括主放大电路200，辅助放大级104包括辅助放大电路202.每个主放大电路 200和辅助放大电路202包括p沟道金属氧化物半导体（PMOS）晶体管T1，T3和n沟道金属氧化物半导体（NMOS）晶体管T2，T4。 辅助放大电路202的PMOS和NMOS晶体管T3，T4与主放大电路200的PMOS和NMOS晶体管T1，T2相同，或者是主放大的PMOS和NMOS晶体管T1，T2的缩小副本 辅助放大电路202放大输入信号以产生控制信号，并且控制器106基于控制信号控制放大器100的功能。

公开(公告)号：WO2016103845A1

公开(公告)日：2016-06-30

申请号：PCT/JP2015/078513

申请日：2015-10-07

Applicant: ソニー株式会社

Inventor： 増田　貴志

IPC: H03K5/24 ,  G01R19/00 ,  H03F3/45 ,  H03K3/0233 ,  H04B10/07

CPC classification number: G01R19/0038 ,  G01R17/02 ,  G01R19/00 ,  H03F3/087 ,  H03F3/45475 ,  H03F2200/405 ,  H03F2200/453 ,  H03F2203/45138 ,  H03F2203/45151 ,  H03F2203/45156 ,  H03F2203/45222 ,  H03K3/0233 ,  H03K5/086 ,  H04B10/69

Abstract: 　信号の有無を正確に検出する。　信号検出器は、入力信号増幅回路、基準信号増幅回路、および、比較器を具備する。この信号検出器において、入力信号増幅回路が、入力信号を所定のゲインにより増幅する。基準信号増幅回路が、所定のゲインに実質的に一致するゲインにより一定の信号レベルの基準信号を増幅する。比較器が、増幅された入力信号と増幅された基準信号とのそれぞれの信号レベルを比較して当該比較結果を検出信号として出力する。

Abstract translation: 在本发明中，信号检测器配备有输入信号放大电路，参考信号放大电路和比较器，以便精确地检测信号的存在。 输入信号放大电路在信号检测器中以预定的增益放大输入信号。 参考信号放大电路经由与预定增益基本匹配的增益放大具有固定信号电平的参考信号。 比较器比较放大的输入信号和放大的参考信号的各个信号电平，并输出比较结果作为检测信号。

公开(公告)号：WO2015160924A1

公开(公告)日：2015-10-22

申请号：PCT/US2015/025934

申请日：2015-04-15

Applicant: THE BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM

Inventor： CHIU, Yun ,  WU, Bo

IPC: H03F1/08 ,  H03F3/45 ,  H03F3/21

CPC classification number: H03F3/45179 ,  H03F1/086 ,  H03F3/211 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/45237 ,  H03F3/4565 ,  H03F2200/153 ,  H03F2200/408 ,  H03F2203/45116 ,  H03F2203/45222 ,  H03F2203/45236 ,  H03F2203/45418 ,  H03F2203/45481

Abstract: Disclosed are systems implementing an implicit Feed-Forward Compensated (FFC) op-amp, where the main FFC port is realized by the P-side (404) of the CMOS input structure of the 2nd (412) and 3rd (414) stages of the op-amp, while the main signal path is through the N-side (402). The 2nd-stage (412) NMOS input pair is split into two pairs, one is used to route the main path while the other is used for auxiliary FFC. The disclosed implicit FCC op-amp is unconditionally stable with adequate phase lead. According to some embodiments, the disclosed op-amp, which may be a wide-band op-amp, can be used in highly linear applications operative at intermediate frequency (IF), such as signal buffers for high-performance data converters or radio-frequency (RF) modulators and demodulators, continuous-time (CT) filters or sigma-delta data converters.

Abstract translation: 公开了实现隐式前馈补偿（FFC）运算放大器的系统，其中主FFC端口由第二（412）和第（414）级的CMOS输入结构的P侧（404）实现 运算放大器，而主信号路径则通过N侧（402）。 第二级（412）NMOS输入对被分成两对，一个用于路由主路径，另一个用于辅助FFC。 所公开的隐式FCC运算放大器是无条件稳定的，具有足够的相位导联。 根据一些实施例，所公开的可以是宽带运算放大器的运算放大器可以用于在中频（IF）下操作的高度线性的应用中，例如用于高性能数据转换器或无线电设备的信号缓冲器， 频率（RF）调制器和解调器，连续时间（CT）滤波器或Σ-Δ数据转换器。