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    POWER DETECTOR WITH TEMPERATURE COMPENSATION
    1.
    发明申请
    POWER DETECTOR WITH TEMPERATURE COMPENSATION 审中-公开
    具有温度补偿功率检测器

    公开(公告)号：WO2013181448A1

    公开(公告)日：2013-12-05

    申请号：PCT/US2013/043445

    申请日：2013-05-30

    Applicant: QUALCOMM INCORPORATED

    Inventor： WANG, Xinwei ,  ZUO, Yongrong ,  ZHANG, Xiangdong ,  DICICCO, Marc Gerald

    IPC: H03F3/24 ,  H03F3/45 ,  G01R21/14

    CPC classification number: H04B17/0062 ,  G01R21/10 ,  G01R21/14 ,  G01R29/0871 ,  H03F3/245 ,  H03F3/45183 ,  H03F3/45188 ,  H03F2200/447 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/465 ,  H03F2203/45112 ,  H03F2203/45156 ,  H03F2203/45292 ,  H03F2203/45302 ,  H03F2203/45481 ,  H03G1/04 ,  H03G3/3036 ,  H04B17/21

    Abstract: Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. Variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor (320), which receives an input signal (Vin), detects the power of the input signal (Vin) based on a power detection gain, and provides an output signal (lout) indicative of the power of the input signal (Vin). The at least one MOS transistor (320) is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor (322) may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.

    Abstract translation: 公开了具有温度补偿并且具有提高的温度精度的功率检测器。 通过改变功率检测器内的MOS晶体管的栅极和漏极电压来降低功率检测器在温度上的增益的变化。 在示例性设计中，一种装置包括至少一个接收输入信号（Vin）的MOS晶体管（320），其基于功率检测增益来检测输入信号（Vin）的功率，并且提供输出信号 ）表示输入信号（Vin）的功率。 至少一个MOS晶体管（320）施加可变栅极偏置电压和可变漏极偏置电压，以便减小功率检测增益随温度的变化。 至少一个附加MOS晶体管（322）可以接收第二可变栅极偏置电压，并为至少一个MOS晶体管提供可变漏极偏置电压。

    AMPLIFIERS WITH IMPROVED LINEARITY AND NOISE PERFORMANCE
    2.
    发明申请
    AMPLIFIERS WITH IMPROVED LINEARITY AND NOISE PERFORMANCE 审中-公开
    具有改进的线性和噪声性能的放大器

    公开(公告)号：WO2011019850A1

    公开(公告)日：2011-02-17

    申请号：PCT/US2010/045223

    申请日：2010-08-11

    Applicant: QUALCOMM INCORPORATED ,  LEE, Hanil ,  CHANG, Li-Chung

    Inventor： LEE, Hanil ,  CHANG, Li-Chung

    IPC: H03F1/22 ,  H03F1/32 ,  H03F3/72 ,  H03F3/21 ,  H03F3/24 ,  H03F3/45 ,  H03G1/00 ,  H04B1/10

    CPC classification number: H03F1/3205 ,  H03F1/223 ,  H03F1/3211 ,  H03F3/211 ,  H03F3/245 ,  H03F3/45179 ,  H03F3/72 ,  H03F2200/294 ,  H03F2200/492 ,  H03F2200/541 ,  H03F2203/45302 ,  H03F2203/45311 ,  H03F2203/45386 ,  H03F2203/45394 ,  H03G1/0029 ,  H04B1/109

    Abstract: Amplifiers with improved linearity and noise performance are described. In an exemplary design, an apparatus includes first through sixth transistors. The first transistor (320) receives an input signal and provides an amplified signal. The second transistor (360) receives the amplified signal and provides signal drive for an output signal. The third transistor (310) receives the input signal and provides an intermediate signal. The fourth transistor (340) provides bias for the third transistor (310) in a high linearity mode. The fifth transistor (350) receives the intermediate signal and provides signal drive for the output signal in a low linearity mode. The third (310) and fourth (340) transistors form a deboost path that is enabled in the high linearity mode to improve linearity. The third (310) and fifth (350) transistors form a cascode path that is enabled in the low linearity mode to improve gain and noise performance. The sixth transistor (330) generates distortion component used to cancel distortion component from the first transistor (320)

    Abstract translation: 描述了具有改善的线性和噪声性能的放大器。 在示例性设计中，装置包括第一至第六晶体管。 第一晶体管（320）接收输入信号并提供放大信号。 第二晶体管（360）接收放大的信号并为输出信号提供信号驱动。 第三晶体管（310）接收输入信号并提供中间信号。 第四晶体管（340）以高线性模式为第三晶体管（310）提供偏置。 第五晶体管（350）接收中间信号，并以低线性模式为输出信号提供信号驱动。 第三（310）和第四（340）晶体管形成在高线性模式下启用的去桥路径，以提高线性度。 第三（310）和第五（350）晶体管形成在低线性模式下使能的共源共栅路径，以改善增益和噪声性能。 第六晶体管（330）产生用于消除来自第一晶体管（320）的失真分量的失真分量，

    ゲイン可変増幅器
    3.
    发明申请
    ゲイン可変増幅器 审中-公开
    可变增益放大器

    公开(公告)号：WO2007105282A1

    公开(公告)日：2007-09-20

    申请号：PCT/JP2006/304796

    申请日：2006-03-10

    Applicant: 富士通株式会社 ,  荒井 知之

    Inventor： 荒井 知之

    IPC: H03G3/10 ,  H03F3/45 ,  H03F3/68

    CPC classification number: H03F3/45188 ,  H03F2203/45052 ,  H03F2203/45302 ,  H03F2203/45311 ,  H03F2203/45361 ,  H03F2203/45364 ,  H03F2203/45366 ,  H03F2203/45396 ,  H03F2203/45544 ,  H03F2203/45616 ,  H03F2203/45638 ,  H03F2203/45726 ,  H03G1/0029 ,  H03G1/0088

    Abstract: 　入力インピーダンスを変化させることなく、増幅器、例えば差動増幅器のゲインを制御可能にすることを目的とし、並列に接続された複数の差動増幅器と、各差動増幅器に対応し、正相差動信号と逆相差動信号との切替を行う複数の信号切替手段とを備え、各信号切替手段の２つの出力が、各差動増幅器の正相入力端子と逆相入力端子に接続され、入力信号として正相差動信号、または逆相差動信号のいずれかを与える。

    Abstract translation: 放大器的增益，例如 差分放大器被控制而不改变输入阻抗。 可变增益放大器包括并联连接的多个差分放大器和分别对应于用于切换正相差分信号和负相位差分信号的差分放大器的多个信号切换装置。 来自每个信号切换装置的两个输出与每个差分放大器的正相输入端子和负相输入端子连接，并且提供正相差分信号或负相位差分信号作为输入信号。

    METHOD AND SYSTEM FOR IMPLEMENTING AUTONOMOUS AUTOMATIC GAIN CONTROL IN A LOW NOISE BROADBAND DISTRIBUTION AMPLIFIER
    4.
    发明申请
    METHOD AND SYSTEM FOR IMPLEMENTING AUTONOMOUS AUTOMATIC GAIN CONTROL IN A LOW NOISE BROADBAND DISTRIBUTION AMPLIFIER 审中-公开
    在低噪声宽带分配放大器中实现自动增益控制的方法和系统

    公开(公告)号：WO2003017476A1

    公开(公告)日：2003-02-27

    申请号：PCT/US2002/025804

    申请日：2002-08-15

    Applicant: BROADCOM CORPORATION

    Inventor： FANOUS, Adel ,  DAUPHINEE, Leonard ,  BURNS, Lawrence, M. ,  MCMULLIN, Donald

    IPC: H03F3/68

    CPC classification number: H03G1/0029 ,  H03F3/45201 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45302 ,  H03F2203/45311 ,  H03F2203/45464 ,  H03F2203/45466 ,  H03F2203/45638 ,  H03F2203/45696 ,  H03G3/3036 ,  H03G3/3052

    Abstract: Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier (308) having a number of first stage input and output ports. The first stage amplifier (308) is configured to provide first stage amplification to a received input signal (RF Input) and produce from the amplified input signal a number of output signals. Also included are a number of second stage amplifiers (310), each having second stage input and output ports, the second stage (310) input ports being respectively coupled to the first stage (308) output ports and being configured to receive the number of output signals. A gain control device (302) is also configured to control a gain of at least one of the first stage amplifier (308) and one or more of the number of second stage amplifiers (310).

    Abstract translation: 提供了一种用于在放大模块中实现增益控制的系统，其包括具有多个第一级输入和输出端口的第一级放大器（308）。 第一级放大器（308）被配置为向接收的输入信号（RF输入）提供第一级放大，并且从放大的输入信号产生多个输出信号。 还包括多个第二级放大器（310），每个第二级放大器具有第二级输入和输出端口，第二级（310）输入端口分别耦合到第一级（308）输出端口，并被配置为接收 输出信号。 增益控制装置（302）还被配置为控制第一级放大器（308）和多个第二级放大器（310）中的至少一个的增益。

    n-BIT CONVERTER WITH n-1 MAGNITUDE AMPLIFIERS AND n COMPARATORS
    5.
    发明申请
    n-BIT CONVERTER WITH n-1 MAGNITUDE AMPLIFIERS AND n COMPARATORS 审中-公开
    具有n-1个放大器和n个比较器的n位转换器

    公开(公告)号：WO1996017437A1

    公开(公告)日：1996-06-06

    申请号：PCT/US1995015467

    申请日：1995-11-29

    Applicant: ANALOG DEVICES, INC.

    Inventor： ANALOG DEVICES, INC. ,  MURDEN, Frank ,  MORELAND, Carl, W.

    IPC: H03M01/44

    CPC classification number: H03F3/26 ,  H03F3/45103 ,  H03F3/45107 ,  H03F2203/45302 ,  H03F2203/45311 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45371 ,  H03F2203/45702 ,  H03F2203/45722 ,  H03M1/445

    Abstract: A serial-type A/D converter that uses magnitude amplifiers ("magamps") and comparators for effecting the conversion of analog signals to Gray scale code signals that are then converted to binary digital signals by a Gray scale code-to-binary portion of the serial-type A/D converter. More specifically, a serial-type A/D converter that uses an n-bit converter that has n-1 magamps and n-comparators. The n-1 magamps are cascaded such that the VOL and VOH outputs of a stage is the inputs to the next stage. The output of the comparators are input to the Gray scale code-to-binary portion of the serial A/D converter. The latching of the comparators occurs outside of the magamps. This allows for the parallel latching of the n comparators. The speed of the serial-type A/D converter is determined by the bandwidth of the magamps. The serial-type A/D converter includes an offset method that significantly reduces the effects of early voltage, VA, on the output waveforms. Each stage of the serial-type A/D converter may have any desired gain and not limited to a particular gain.

    Abstract translation: 一种使用幅度放大器（“magamps”）和比较器的串行型A / D转换器，用于将模拟信号转换为灰度代码信号，然后通过灰度代码到二进制部分转换为二进制数字信号 串行型A / D转换器。 更具体地，是使用具有n-1个magamp和n比较器的n位转换器的串行型A / D转换器。 级联的n-1型卡子使得一级的VOL和VOH输出是下一级的输入。 比较器的输出被输入到串行A / D转换器的灰度代码到二进制部分。 比较器的锁存发生在卡盘之外。 这允许n个比较器的并联闭锁。 串行型A / D转换器的速度由卡盘的带宽决定。 串行型A / D转换器包括一种偏移方法，可显着降低早期电压VA对输出波形的影响。 串行型A / D转换器的每个级可以具有任何期望的增益，而不限于特定的增益。

    AMPLIFIER SUPPORTING MULTIPLE GAIN MODES
    8.
    发明申请
    AMPLIFIER SUPPORTING MULTIPLE GAIN MODES 审中-公开
    放大器支持多种增益模式

    公开(公告)号：WO2010111297A1

    公开(公告)日：2010-09-30

    申请号：PCT/US2010/028353

    申请日：2010-03-23

    Applicant: QUALCOMM INCORPORATED ,  MUTHALI, Harish, S. ,  XIONG, Zhijie

    Inventor： MUTHALI, Harish, S. ,  XIONG, Zhijie

    IPC: H03F3/45 ,  H03G1/00 ,  H03F1/26 ,  H03F1/32 ,  H03F3/21 ,  H03F3/72 ,  H03F3/195 ,  H03F1/22

    CPC classification number: H03F1/223 ,  H03F1/26 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/211 ,  H03F3/45188 ,  H03F3/72 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45302 ,  H03F2203/45386 ,  H03F2203/7206 ,  H03G1/0029 ,  H03G1/0088

    Abstract: Techniques for designing a low-noise amplifier (LNA) for operation over a wide range of input power levels. In an exemplary embodiment, a first gain path is provided in parallel with a second gain path. The first gain path includes a differential cascode amplifier with inductor source degeneration. The second gain path includes a differential cascode amplifier without inductor source degeneration. The cascode transistors of the gain paths may be selectively biased to enable or disable the first and/or second gain path. By selectively biasing the cascode transistors and input transistors, various combinations of the first and second gain paths may be selected to provide an optimized gain configuration for any input power level.

    Abstract translation: 用于设计低噪声放大器（LNA）的技术，用于在宽范围的输入功率电平下工作。 在示例性实施例中，与第二增益路径并行地提供第一增益路径。 第一增益路径包括具有电感源退化的差分共源共栅放大器。 第二增益路径包括没有电感源退化的差分共源共栅放大器。 可以选择性地偏置增益路径的共源共栅晶体管，以启用或禁用第一和/或第二增益路径。 通过选择性地偏置共源共栅晶体管和输入晶体管，可以选择第一和第二增益路径的各种组合来为任何输入功率电平提供优化的增益配置。

    VOLTAGE REGULATOR WITH HIGH GAIN CASCODE MIRROR
    10.
    发明申请
    VOLTAGE REGULATOR WITH HIGH GAIN CASCODE MIRROR 审中-公开
    具有高增益镜像的电压调节器

    公开(公告)号：WO1993016427A1

    公开(公告)日：1993-08-19

    申请号：PCT/US1993001084

    申请日：1993-02-08

    Applicant: CROSSPOINT SOLUTIONS, INC.

    Inventor： CROSSPOINT SOLUTIONS, INC. ,  ALLMAN, Gary, L.

    IPC: G05F01/59

    CPC classification number: H03F3/45076 ,  G05F3/262 ,  G05F3/30 ,  H03F3/45188 ,  H03F2203/45302 ,  H03F2203/45508 ,  H03F2203/45654 ,  H03F2203/45674 ,  Y10T307/696

    Abstract: The present invention provides a voltage regulator (71) especially adaptable for use with a field-programmable gate array (FPGA). The voltage regulator of the present invention rapidly generates an operating voltage for the core or nucleus logic elements upon application of external power while preventing degradation of the fuses. The core or regulated voltage of an FPGA can be set to a level that provides maximum performance with minimum power consumption or, alternatively, permits propagation delays and switching rates to be adjusted so as to compensate for die to die variation. Since it is common for electrical parameters of FPGA manufactured in different wafer fabrication facilities to vary, the voltage regulator (71) is configurable as a true voltage regulator providing its output through a switching transistor (198) or, alternatively, as a pseudo-voltage regulator providing its output through a switching transistor (188).

    Abstract translation: 本发明提供一种特别适用于现场可编程门阵列（FPGA）的电压调节器（71）。 本发明的电压调节器在施加外部功率时快速地产生用于芯或核逻辑元件的工作电压，同时防止保险丝的劣化。 FPGA的核心或调节电压可以设置为以最小功耗提供最大性能的水平，或者允许调整传播延迟和开关速率以补偿管芯到管芯的变化。 由于在不同的晶片制造设备中制造的FPGA的电参数通常是变化的，因此电压调节器（71）可配置为真正的电压调节器，其通过开关晶体管（198）提供其输出，或者作为伪电压 调节器通过开关晶体管（188）提供其输出。

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