Abstract:
An instrumentation amplifier that includes input capacitance cancellation is provided. The architecture includes programmable capacitors between the input stage and a current feedback loop of the instrumentation amplifier to cancel input capacitances from electrode cables and a printed circuit board at the front end. An on-chip calibration unit can be employed to calibrate the programmable capacitors and improve the input impedance.
Abstract:
A differential amplifier has at least two pairs of active devices, one pair being connected as the load for the other pair. The outputs are taken at the nodes between the two pairs of amplifiers. With appropriate biasing, this amplifier provides improved noise and gain performance.
Abstract:
Exemplary embodiments of the disclosure include adaptively generating a bias current for a switched-capacitor circuit. An exemplary apparatus includes a first phase signal and a second phase signal operating at a sampling rate. An asserted time of the first phase signal and an asserted time of the second phase signal are separated by a predefined non-overlap time. The apparatus also includes a switched-capacitor circuit with a plurality of switched capacitors operably coupled to the first phase signal and the second phase signal. An amplifier is operably coupled to the switched-capacitor circuit and has a response time inversely proportional to an adaptive bias current. A bias generator is coupled to the amplifier and operates to modify the adaptive bias current responsive to the asserted time of the first phase signal.
Abstract:
L'invention concerne un dipôle passif résistif (30) réalisé sous forme monolithique constitué d'une association en série et/ou parallèle d'au moins deux éléments mémoire magnéto-résistifs (31, 32, 33, 34).
Abstract:
Die Erfindung betrifft einen Spannungsverstärker (100, 300), der definierte Bereiche (12, 14) eines Eingangsspannungssignals (10) in unterschiedliche Bezüge im Verhältnis zum Eingangsspannungssignal (10) zu einem oder mehreren Arbeitspunkten einer Verstärkerschaltung (130) setzt. Bei entsprechender Aufteilung der Bereiche (12, 14) des Eingangsspannungssignals (10) ist es möglich, die jeweiligen Bereiche (12, 14) linear zu verstärken. Solche linear verstärkten Ausgangssignale (191, 192, 193, 194) können sodann zum Beispiel mittels mehrerer Analog-Digital-Wandler (510) in digitale Signale (531) umgewandelt werden.
Abstract:
An apparatus relating generally to voltage conversion includes an amplifier (101) coupled to receive an input voltage (121) and a reference voltage (122). First and second converters (111, 112) are coupled to the amplifier (101) to receive a bias voltage (102). The first converter (111) includes a first transconductor (131) coupled to receive the bias voltage (102) to adjust a first tail current, and a first differential input (117P, 117M). A first inverter (141) of the first converter (111) has a first feedback device (145) coupled input-to-output to provide a first transimpedance amplifier load. The first inverter (141 ) is coupled to the first transconductor (131). The second converter (112) includes a second transconductor (132) coupled to receive the bias voltage (102) to adjust a second tail current, and a second differential input (117M, 117P). A second inverter (142) of the second converter (112) has a second feedback device (145) coupled input-to-output to provide a second transimpedance amplifier load. The second inverter (142) is coupled to the second transconductor (132).
Abstract:
To provide a semiconductor device with low power consumption, in a semiconductor device including a differential amplifier to which an input potential and a reference potential are input, a gain stage, and an output stage from which an output potential is output, a potential supplied from the gain stage can be held constant by providing the output stage with a transistor with low leakage current in an off state. As the transistor with low leakage current in an off state, a transistor including an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer is used.
Abstract:
An active over-voltage clamp system includes at least one over-voltage detector that is responsive to an input voltage and provides a first current. The system also includes a replica over-voltage circuit that provides a second current, and circuitry subtracting the second current from the first current to produce a difference current. The system further includes a differential clamp activated in response to the difference current. The differential clamp prevents the input voltage from increasing beyond a target voltage.