Abstract:
Method, apparatus, and systems employing novel dictionary entry replacement schemes for dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.
Abstract:
A method and apparatus in a data processing system for encoding a data packet. The method and apparatus provide for the generation of data in the form of integers, conversion of the data into a first factorial vector (FVo) in a predetermined range of factorial vectors and defining a series of objects, variables and operators. The data is then mapped to a permutation of objects such that each data packet is mapped to a unique permutation of objects.
Abstract:
A digital coding process for transmitting and/or storing acoustic signals, in particular musical signals, in which N pick-up values of the acoustic signal are transformed into M spectral coefficients. The process is characterised by the fact that in a first stage the M spectral coefficients are quantified. After coding, an optimal coder checks the number of bits necessary for reproduction. If the number of bits is above a predetermined number, the quantification and coding are repeated in further stages until the number of bits necessary for reproduction no longer exceeds the predetermined number of bits. The required quantification stage is transmitted or stored in addition to the data bits. The advantage of the process is that acoustic signals in particular musical signals, can be transmitted and/or recorded without any subjective quality reduction of the musical signals with a reduction of data rate by factors of 4 to 6.
Abstract:
An apparatus and method are described for reducing power when reading and writing graphics data. For example, one embodiment of an apparatus comprises: a graphics processor unit (GPU) to process graphics data including floating point data; a set of registers, at least one of the registers of the set partitioned to store the floating point data; and encode/decode logic to reduce a number of binary 1 values being read from the at least one register by causing a specified set of bit positions within the floating point data to be read out as 0s rather than 1s.
Abstract:
Disclosed herein is a method of generating a coded data packet in dependence on a plurality of source data packets, the method comprising: determining a plurality of data packets, for generating a coded data packet, from a plurality of source data packets for encoding, wherein each of the plurality of source data packets for encoding comprises the same number of bits; generating a multiplied data packet in dependence on one or more multiplication operations between a multiplication value and bits of one of the determined data packets; and generating a coded data packet in dependence on a combination of the multiplied data packet and one or more of the other of said plurality of determined data packets that have not been multiplied; wherein the one or more multiplication operations are performed as operations in the finite field GF (p); p is greater than 2; the multiplication value is an element of the finite field GF (p); the multiplication value is not 0 or 1; and the combination of data packets is performed by bitwise XOR operations. Advantageously, the coding scheme can be almost as computationally efficient as GF (2) and the likelihood of obtained coded data packets being linearly independent is greatly increased.
Abstract:
Изобретение относится к способу преобразования (кодирования), декодирования и записи цифровой информации для формирования матричного ультрасжатого двухмерного кода (нанобар-кода), а также к оптически считываемым двухмерным кодам, представляющим двоично-кодированные данные, размещенные на двухмерной матрице и формирующие, таким образом, шаблон для размещения информации. Основной целью изобретения является разработка способа кодирования и декодирования цифровой информации в виде ультрасжатого нанобар-кода, с возможностью шифрования информации, устойчивого к повреждениям и имеющего множество вариантов реализации. Технический результат заключается в повышении надежности кодирования информации за счет введения операции шифрования, а также возможности восстановления данных в случае их утери.
Abstract:
The invention relates to a method for creating a bit stream from an indexing tree comprising a plurality of hierarchical levels, to each of which one or several index nodes are assigned. Said index nodes contain index data which is sorted in the indexing tree according to one or several given criteria. According to the inventive method, the index data of the index nodes is inserted into the bit stream, and the information concerning the position within the bit stream, where the index data of one or several index nodes of the hierarchical level located below the hierarchical level of the respective node is situated, is inserted into the bit stream for an index node.
Abstract:
A signal converter is provided for converting multiple level encoded digital signals into a binary equivalent signal. The signal converter includes a reference voltage generator, a plurality of four-input differential comparators, timing recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are each operative to compare magnitude of a differential input voltage with magnitude of a dedicated one of the progressively larger differential reference voltages and produce a differential output voltage having a first logical sense if the magnitude of the differential input voltage is greater than the magnitude of the differential reference voltage, and having a second logical sense if the magnitude of the differential input voltage is less than the magnitude of the differential reference voltage. Each comparator has an offset input voltage. The timing recovery circuitry is configured to receive the differential output voltages from each of the differential comparators and is operative to derive a clock via edge detection and generate a recovered clock signal. The signal conversion circuitry is coupled with the timing recovery circuitry and the differential comparators and is operative to convert the differential output voltages into a binary equivalent. A method is also provided.