Abstract:
Methods, systems, and apparatuses for defending against cryptographic attacks using clock period randomization. The methods, systems, and apparatuses are designed to make side channel attacks and fault injection attacks more difficult by using a clock with a variable period during a cryptographic operation. In an example embodiment, a clock period randomizer includes a fixed delay generator and a variable delay generator, wherein a variable delay generated by the variable delay generator is based on a random or pseudorandom value that is changed occasionally or periodically. The methods, systems, and apparatuses are useful in hardware security applications where fault injection and/or side channel attacks are of concern.
Abstract:
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus may be used for detecting an incorrect clock frequency. In one example, the apparatus includes a first circuit configured to compare a clock signal period to a delay period. Additionally, in one example, the apparatus includes a second circuit configured to output a first signal. The period of the first signal may be double the clock signal period when the clock signal period is greater than the delay period. The apparatus may, in one example, also include a third circuit configured to output a second signal. The period of the second signal may be greater than double the clock signal period when the clock signal period is greater than the delay period.
Abstract:
A cryptography machine, method and computer-readable storage medium with instructions for replacing an S-box substitution followed by a linear transformation with one of more lookup tables when performing a cryptography operation, for example, a cryptography operation of the SMS4 algorithm. Other systems and methods are disclosed.
Abstract:
The invention provides a method for carrying out a cryptographic calculation comprising a plurality of blocks, in a manner protected against spying of secret data, using secret data in a processor. In order to achieve a calculation result, a multiple calculation is carried out, during which the calculation is carried out several times, at least twice. Within the multiple calculation, blocks of the plurality of, at least two, operations of carrying out the calculation are carried out in interleaved order.
Abstract:
The present invention relates to cryptographic method that are resistant to fault injection attacks, to protect the confidentiality and the integrity of secret keys. For that, the invention describes a method to protect a key hardware register against fault attack, this register being inside an hardware block cipher BC embedded inside an electronic component, said component containing stored inside a memory area a cryptographic key K, characterized in that it comprises following steps: A.) loading the key Kram inside said register; B.) computing a value X such as K=BC(K,X); C.) after at least one sensitive operation, computing a value V such as V=BC(K,X); D.) matching the value V with the key Kram value stored in the memory area; E.) if the matching is not ok detecting that a fault occurs.
Abstract:
The invention relates to a method for protecting a microcircuit (12) from attacks for obtaining secret data (K, M) used when the microcircuit runs a cryptography algorithm (10). Said method comprises a step of generating at least one parameter (P) for protecting the secret data (K, M), and a step of modifying the running of the cryptography algorithm by means of said protection parameter (P). Said method comprises steps of defining a generating function (20' a) by successively applying, to at least one pre-determined secret parameter (S) stored in the memory (16), a sequence of values that can be determined only from said secret parameter (S) and said function (20' a), and of reproducibly generating the protection parameter (P) from at least one value of said sequence.
Abstract:
An information security transmission system is provided, which includes a first information device and a second information device. The first information device obtains at least authentication information and connects with the second information device via a network for information exchange. The system obtains the key pairs for encryption and decryption with or without the help of certification center, builds an information transmission security channel, encrypts and decrypts for the transmitted information and keeps the security of the transmitted information. The first information device has a first dynamic encoder/decoder and the second information device has a second dynamic encoder/decoder respectively. The first dynamic encoder/decoder and the second first dynamic encoder/decoder encode dynamically and ensure a one-time completion of error-free transmission and safety of the transmitted information with mechanism of auto error-detection and mechanism of auto error-correction. And the transmitted information has an access limitation, which makes the receiving party access the transmitted information in the limitation of an accessing condition and delete all the transmitted information when exceeding the accessing limitation so as to prevent the transmitted information from out-flowing.
Abstract:
中国人剰余定理(CRT)を用いたRSA復号処理を行う暗号処理装置であって、前記RSA復号処理は、暗号文を c 、法を n 、秘密鍵を d とおくと、 c d (mod n) で表され、また、法 n は二つの素数 p 、 q を用いて n = p×q と表されるものであって、乱数 r を用意する乱数生成手段と、前記p 、 q を法とする指数剰余演算を実行した後に平文を計算するステップにおいて前記乱数 r に応じて u = p -1 (mod q) を用いた計算方式かもしくは v = q -1 (mod p) を用いた計算方式かのいずれかを選択する復号化経路選択手段と、を含む暗号処理装置。