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    HIGH-TEMPERATURE JOSEPHSON JUNCTION AND METHOD
    1.
    发明申请
    HIGH-TEMPERATURE JOSEPHSON JUNCTION AND METHOD 审中-公开
    高温JOSEPHSON接头和方法

    公开(公告)号：WO1994025969A1

    公开(公告)日：1994-11-10

    申请号：PCT/US1994004674

    申请日：1994-04-28

    Applicant: VARIAN ASSOCIATES, INC.

    Inventor： VARIAN ASSOCIATES, INC. ,  BOZOVIC, Ivan ,  ECKSTEIN, James, N. ,  KLAUSMEIER-BROWN, Martin, E. ,  VIRSHUP, Gary, F.

    IPC: H01B12/00

    CPC classification number: H01L39/225 ,  Y10S505/702 ,  Y10S505/729

    Abstract: A hysteretic high-T.sub.C. trilayer Josephson junction (10), and a method of forming the same are disclosed. The junction includes lower and upper high-T.sub.C superconducting cuprate films (18, 22) separated by a barrier layer (20), where the thin films each include a molecular junction layer adjacent the barrier layer which is characterized by a high-T.sub.C cuprate stoichiometry and crystal structure, and a flat two-dimensional surface, as evidenced by its electron diffraction pattern using reflected high-energy electron diffraction. The junction and barrier layers in the junction are formed by atomic layer-by-layer deposition.

    Abstract translation: 一个迟滞的高T.sub.C。 三层约瑟夫逊结（10）及其形成方法。 该接合点包括由阻挡层（20）分开的下部和上部高T.sub.C超导铜酸盐膜（18,22），其中薄膜各自包括邻近阻挡层的分子结层，其特征在于高 -T.sub.C铜酸盐化学计量和晶体结构，以及平坦的二维表面，如使用反射的高能电子衍射的电子衍射图所证明的。 结中的结和阻挡层通过原子层逐层沉积形成。

    ELECTRON DEVICE HAVING A CURRENT CHANNEL OF DIELECTRIC MATERIAL
    2.
    发明申请
    ELECTRON DEVICE HAVING A CURRENT CHANNEL OF DIELECTRIC MATERIAL 审中-公开
    具有电流材料的电流通道的电子器件

    公开(公告)号：WO1991015033A1

    公开(公告)日：1991-10-03

    申请号：PCT/JP1991000372

    申请日：1991-03-20

    Applicant: FUJITSU LIMITED ,  TAMURA, Hirotaka

    Inventor： FUJITSU LIMITED

    IPC: H01L45/00

    CPC classification number: H01L45/00 ,  Y10S505/702

    Abstract: An electron device comprises a first dielectric layer (103) having a first thickness determined to allow the tunneling of carriers therethrough and a first dielectric constant, a second dielectric layer (104) provided in contact with the first dielectric layer, the second dielectric layer having a second thickness substantially larger than the first thickness and a second dielectric constant that is substantially larger than the first dielectric constant, a first electrode (101) provided on the first dielectric layer for injecting the carriers, and a second electrode (108) provided in contact with the second dielectric layer for controlling a flow of the carriers through the second dielectric layer in response to a control voltage supplied thereto.

    Abstract translation: 电子器件包括：第一介电层（103），其具有确定允许载流子穿透其中的第一厚度和第一介电常数;第二介电层（104），设置成与第一介电层接触;第二介电层具有 基本上大于所述第一厚度的第二厚度和基本上大于所述第一介电常数的第二介电常数;设置在所述第一电介质层上用于注入载流子的第一电极（101）和设置在所述第二电极 与第二电介质层接触，用于响应于提供给其的控制电压来控制载流子通过第二介电层的流动。

    IMPROVED BARRIER LAYERS FOR OXIDE SUPERCONDUCTOR DEVICES AND CIRCUITS
    4.
    发明申请
    IMPROVED BARRIER LAYERS FOR OXIDE SUPERCONDUCTOR DEVICES AND CIRCUITS 审中-公开
    用于氧化物超导体器件和电路的改进的障碍层

    公开(公告)号：WO1994007270A1

    公开(公告)日：1994-03-31

    申请号：PCT/US1993008657

    申请日：1993-09-14

    Applicant: CONDUCTUS, INC. ,  CHAR, Kookrin ,  GEBALLE, Theodore, H.

    Inventor： CONDUCTUS, INC.

    IPC: H01L39/22

    CPC classification number: H01L39/225 ,  H01L27/18 ,  Y10S505/702 ,  Y10S505/781

    Abstract: A conductor suitable for use in oxide-based electronic devices and circuits is disclosed. Metallic oxides having the general composition AMO3, where A is a rare or alkaline earth or an alloy of rare or alkaline earth elements, and M is a transition metal, exhibit metallic behavior and are compatible with high temperature ceramic processing. Other useful metallic oxides have compositions (A1-xA'x)B2(M1-yM'y)3O7-(delta) or (A1-xA''x)m(M1-yM'y)nO2m+n, where 0

    Abstract translation: 公开了一种适用于氧化物基电子器件和电路的导体。 具有一般组成AMO3的金属氧化物，其中A是稀土或碱土金属或稀土或碱土金属的合金，M是过渡金属，具有金属性能并与高温陶瓷加工兼容。 其他有用的金属氧化物具有组成（A1-xA'x）B2（M1-yM'y）3O7-（delta）或（A1-xA'x）m（M1-yM'y）nO2m + n，其中0 < = x，y <= 1和0.5 <= m，n <= 3，A和A'是稀土或碱土或稀土或碱土的合金，A“和B”是碱土金属，碱土金属 元素，稀土元素，稀土元素合金或碱土金属和稀土元素的合金，M和M'是过渡金属元素或过渡金属元素的合金。 金属氧化物在氧化物超导体以及通常用于生长氧化物超导体的衬底和缓冲层上外延生长。 氧化物超导体也可以外延生长在这些金属氧化物上。 当正常材料是所公开的类型的金属氧化物时，可以获得高温超导体材料中超导体 - 正常超导体（SNS）结的性能的大幅提高。 在优选实施方案中，导电氧化物CaRuO 3用作作为超导体的YBa2Cu3O7-（delta）的SNS结中的正常材料。 在这种类型的接合处制造的77K功能的直流超导量子干涉器件（SQUID）表现出大的调制和低噪声。

    DEVICES FROM AND METHOD FOR PRODUCING CRYSTALLOGRAPHIC BOUNDARY JUNCTIONS IN SUPERCONDUCTING THIN FILMS
    6.
    发明申请
    DEVICES FROM AND METHOD FOR PRODUCING CRYSTALLOGRAPHIC BOUNDARY JUNCTIONS IN SUPERCONDUCTING THIN FILMS 审中-公开
    在超薄膜中制造晶体间界面结构的装置和方法

    公开(公告)号：WO1992015406A1

    公开(公告)日：1992-09-17

    申请号：PCT/US1992001444

    申请日：1992-02-24

    Applicant: SUPERCONDUCTOR TECHNOLOGIES, INC.

    Inventor： SUPERCONDUCTOR TECHNOLOGIES, INC. ,  JAMES, Timothy, Walton ,  FLEMING, Julia, Sophia

    IPC: B05D05/12

    CPC classification number: H01L39/225 ,  H01L39/2496 ,  Y10S505/701 ,  Y10S505/702 ,  Y10S505/728 ,  Y10S505/732

    Abstract: Devices from and a method for generating repeatable and reproducible crystallographic grain-boundary junctions are provided by forming a film on a crystalline substrate which has intersecting faces. In a preferred embodiment, a single crystal substrate (10) is etched by an anisotropic etchant to provide a ''V''-groove in one face, and an epitaxial superconducting film (16) is grown on the faces (14) of the V-groove. In another preferred embodiment, a step is etched with an anisotropic etch, and an epitaxial superconducting film grown on the step. Grain-boundary junctions are formed at the points (20) of intersection of the faces with each other, or with the faces (18) and the surface of the substrate. The film may be patterned and etched in the area of the boundary junction to form useful devices. One useful device is a SQUID formed with the boundary junction at the bottom of a V-groove. Another useful device is serially connected junctions.

    Abstract translation: 通过在具有相交面的晶体衬底上形成膜来提供用于产生可重复和可再现的结晶晶界结的装置和方法。 在优选实施例中，通过各向异性蚀刻剂对单晶衬底（10）进行蚀刻，以在一个面中提供“V”形槽，并且外延超导膜（16）生长在 V形槽。 在另一优选实施例中，通过各向异性蚀刻蚀刻步骤，并在该步骤上生长外延超导膜。 在面彼此相交的点（20）处，或者与面（18）和衬底的表面相交的点（20）处形成晶界结。 该膜可以在边界结的区域中被图案化和蚀刻以形成有用的装置。 一个有用的装置是在V形槽的底部形成边界结的SQUID。 另一个有用的装置是串联的连接点。

    IMPRINT LITHOGRAPHY FOR SUPERCONDUCTOR DEVICES
    10.
    发明申请
    IMPRINT LITHOGRAPHY FOR SUPERCONDUCTOR DEVICES 审中-公开
    超导体器件的印刷图

    公开(公告)号：WO2005006456A1

    公开(公告)日：2005-01-20

    申请号：PCT/US2004/013532

    申请日：2004-04-29

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. ,  STASIAK, James ,  KORNILOVICH, Pavel

    Inventor： STASIAK, James ,  KORNILOVICH, Pavel

    IPC: H01L39/24

    CPC classification number: G06N99/002 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L39/2493 ,  Y10S505/702 ,  Y10S977/933 ,  Y10T29/49014

    Abstract: One aspect of this disclosure relates to a method of building a superconductor device (50) on a substrate (306), comprising depositing an imprint layer (304) on at least a portion of the substrate (306). The imprint layer (304) is imprinted to provide an imprinted portion (503) of the imprint layer (304) and a non-imprinted portion (504) of the imprint layer (304). A superconductor layer (310) is deposited on at least a portion of the imprinted portion (503) of the imprint layer (304).

    Abstract translation: 本公开的一个方面涉及在衬底（306）上构建超导体器件（50）的方法，包括在衬底（306）的至少一部分上沉积压印层（304）。 压印层（304）被压印以提供压印层（304）的压印部分（503）和压印层（304）的非压印部分（504）。 超导体层（310）沉积在压印层（304）的压印部分（503）的至少一部分上。

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