公开(公告)号：WO1994020224A1

公开(公告)日：1994-09-15

申请号：PCT/US1994002393

申请日：1994-03-01

Applicant: THE DEXTER CORPORATION

Inventor： THE DEXTER CORPORATION ,  GALLO, Anthony, A.

IPC: B05D05/12

CPC classification number: H01L23/293 ,  C08G59/30 ,  C08K3/22 ,  C08L63/00 ,  H01L2924/0002 ,  Y10T428/31511 ,  C08L61/04 ,  H01L2924/00

Abstract: A flame retardant epoxy molding compound comprises an epoxy, a hardener preferably of the novolac or anhydride type, a catalyst, a mold release agent, preferably a filler, preferably a colorant, preferably a coupling agent, an organic compound containing a halogen (which can be part of the resin or the hardener), and an oxidizing refractory metal oxide, preferably an oxidizing metal oxide of an element selected from the Group VIA of the Periodic Table. The flame retardant epoxy molding compounds when used to encapsulate semiconductor devices have synergistic flame retardant properties.

Abstract translation: 阻燃性环氧树脂模塑料包括环氧树脂，优选酚醛清漆或酸酐型的硬化剂，催化剂，脱模剂，优选填料，优选着色剂，优选偶联剂，含有卤素的有机化合物（其可以 作为树脂或固化剂的一部分）和氧化性难熔金属氧化物，优选选自元素周期表第VIA族元素的氧化性金属氧化物。 用于封装半导体器件的阻燃环氧模塑料具有协同的阻燃性能。

公开(公告)号：WO1993019857A1

公开(公告)日：1993-10-14

申请号：PCT/US1993002990

申请日：1993-03-30

Applicant: VISTATECH CORPORATION

Inventor： VISTATECH CORPORATION ,  RAINWATER, Jewel, G.

IPC: B05D05/12

CPC classification number: H01L21/67236 ,  H01G4/308 ,  H01L21/4857 ,  H01L21/4867 ,  H05K3/4664

Abstract: A method for making a substrate for use in a multilayered integrated circuit or multichip module which includes coating a conductive material (14) on a surface of a support sheet (10) to form a conductive circuit (12) and then drying the sheet. Next, a coating of a layer of dielectric layer (18) is placed on the support surface in the areas where the conductive material is not cast. After which the coated sheet is densified to form a densified conductive circuit embedded dielectric layer. A second coating of a dielectric (28) is placed over the first densified conductive circuit embedded dielectric layer such that the second layer is characterized by vias (30) therein which are in register with at least a portion of the conductive circuit (12). The vias in the second dielectric layer are filled to form electrically conductive vias and then densified to form the substrate (44).

Abstract translation: 一种制造用于多层集成电路或多芯片模块的衬底的方法，包括在支撑片（10）的表面上涂覆导电材料（14）以形成导电电路（12），然后干燥片材。 接下来，将电介质层（18）的涂层放置在导电材料不被铸造的区域中的支撑表面上。 之后，将被覆层片致密化，形成致密化的导电电路嵌入介质层。 电介质（28）的第二涂层被放置在第一致密化的导电电路嵌入介电层上，使得第二层的特征在于其中与导电电路（12）的至少一部分对准的通孔（30）。 填充第二电介质层中的通孔以形成导电通孔，然后致密化以形成衬底（44）。

公开(公告)号：WO1992015406A1

公开(公告)日：1992-09-17

申请号：PCT/US1992001444

申请日：1992-02-24

Applicant: SUPERCONDUCTOR TECHNOLOGIES, INC.

Inventor： SUPERCONDUCTOR TECHNOLOGIES, INC. ,  JAMES, Timothy, Walton ,  FLEMING, Julia, Sophia

IPC: B05D05/12

CPC classification number: H01L39/225 ,  H01L39/2496 ,  Y10S505/701 ,  Y10S505/702 ,  Y10S505/728 ,  Y10S505/732

Abstract: Devices from and a method for generating repeatable and reproducible crystallographic grain-boundary junctions are provided by forming a film on a crystalline substrate which has intersecting faces. In a preferred embodiment, a single crystal substrate (10) is etched by an anisotropic etchant to provide a ''V''-groove in one face, and an epitaxial superconducting film (16) is grown on the faces (14) of the V-groove. In another preferred embodiment, a step is etched with an anisotropic etch, and an epitaxial superconducting film grown on the step. Grain-boundary junctions are formed at the points (20) of intersection of the faces with each other, or with the faces (18) and the surface of the substrate. The film may be patterned and etched in the area of the boundary junction to form useful devices. One useful device is a SQUID formed with the boundary junction at the bottom of a V-groove. Another useful device is serially connected junctions.

Abstract translation: 通过在具有相交面的晶体衬底上形成膜来提供用于产生可重复和可再现的结晶晶界结的装置和方法。 在优选实施例中，通过各向异性蚀刻剂对单晶衬底（10）进行蚀刻，以在一个面中提供“V”形槽，并且外延超导膜（16）生长在 V形槽。 在另一优选实施例中，通过各向异性蚀刻蚀刻步骤，并在该步骤上生长外延超导膜。 在面彼此相交的点（20）处，或者与面（18）和衬底的表面相交的点（20）处形成晶界结。 该膜可以在边界结的区域中被图案化和蚀刻以形成有用的装置。 一个有用的装置是在V形槽的底部形成边界结的SQUID。 另一个有用的装置是串联的连接点。

公开(公告)号：WO1992006798A1

公开(公告)日：1992-04-30

申请号：PCT/US1991007381

申请日：1991-10-03

Applicant: SUPERCONDUCTOR TECHNOLOGIES, INC.

Inventor： SUPERCONDUCTOR TECHNOLOGIES, INC. ,  JAMES, Timothy, Walton ,  NILSSON, Boo, Jorten, Lars

IPC: B05D05/12

CPC classification number: H01L39/2448 ,  C23C14/087 ,  C30B23/002 ,  C30B23/02 ,  C30B29/22 ,  C30B29/225 ,  Y10S505/73 ,  Y10S505/732

Abstract: In situ vapor phase growth of thallium containing superconductors is achieved by controlling thallium volatility. Thallium volatility is controlled by providing active oxygen at the surface of the growing material and by avoiding collisions of energetic species with the growing material. In the preferred embodiment, a thallium containing superconductor is grown by laser ablation of a target, and by provision of oxygen during growth. More specificially, a source of thallium, calcium, barium, copper and oxygen is created by laser ablation of a thallium rich target (20), generating an ablation plume (36) that is directed onto a heated substrate (12) through the oxygen, with the plume passing through oxygen having a pressure from 10 to ten torr. Epitaxial superconducting thin films of thallium, calcium, barium, copper and oxygen have been grown by this technique. Various superconducting phases may be engineered through use of this method.

Abstract translation: 通过控制铊挥发性来实现含铊超导体的原位气相生长。 铊挥发性通过在生长材料的表面提供活性氧并通过避免能量物种与生长材料的碰撞来控制。 在优选实施例中，含铊的超导体通过靶的激光烧蚀和生长期间的氧气生长。 更具体地，铊，钙，钡，铜和氧的来源通过富铊靶（20）的激光烧蚀产生，产生通过氧引导到加热的衬底（12）上的消融羽流（36） 其中羽流通过氧气，压力为10 -2至10托。 已经通过这种技术生长了铊，钙，钡，铜和氧的外延超导薄膜。 可以通过使用这种方法来设计各种超导相。

公开(公告)号：WO1991017840A1

公开(公告)日：1991-11-28

申请号：PCT/US1991003257

申请日：1991-05-13

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY ,  DUDEK, Dietmar ,  PFEIFFER, Thomas ,  JENSEN, Richard, H. ,  HAFNER, Carola

Inventor： E.I. DU PONT DE NEMOURS AND COMPANY

IPC: B05D05/12

CPC classification number: H05K3/207 ,  H05K1/0306 ,  H05K3/102 ,  H05K2203/0525 ,  H05K2203/1131

Abstract: A process for producing conductor lines for electrical circuits, which process enables high packing density of the conductor lines and is adaptable to a large number of different conductors and support materials. The process comprises producing a powder image of a conductor line pattern by means of a preferably photographically prepared, positive, tacky pattern on an intermediate support; removing the tacky pattern, and transferring the powder image onto a final support, the powder image being consolidated into a conductor line pattern either before or after the transfer by sintering.

公开(公告)号：WO1984003645A1

公开(公告)日：1984-09-27

申请号：PCT/US1984000397

申请日：1984-03-16

Applicant: W. L. GORE & ASSOCIATES, INC

Inventor： W. L. GORE & ASSOCIATES, INC ,  MANNISO, James, L.

IPC: B05D05/12

CPC classification number: B01D67/0088 ,  B01D46/00 ,  B01D46/10 ,  B01D53/00 ,  B01D53/8637 ,  B01D67/0069 ,  B01D69/12 ,  B01D71/022 ,  B01D2325/26 ,  B01D2325/36 ,  B01D2325/38 ,  C23C18/1644 ,  C23C18/2086 ,  C23C18/285 ,  C23C18/30 ,  D06M11/83 ,  H01M4/80 ,  H01M4/86 ,  H05K1/034 ,  H05K9/0084 ,  H05K9/0088 ,  H05K9/009 ,  Y10T428/1355 ,  Y10T428/24942 ,  Y10T428/24967 ,  Y10T428/249978 ,  Y10T428/249979 ,  Y10T428/249981 ,  Y10T428/31544 ,  Y10T428/31692

Abstract: Microporous polytetrafluoroethylene (PTFE) articles (12, 14, 16), having a microstructure of nodes interconnected by fibrils also having continuous interporous metal coating which encapsulate the nodes and fibrils of the PTFE while maintaining substantial porosity, together with a method of producing temporary liquid filled hydrophilic microporous article resulting in an improved metal plating manufacturing process.

公开(公告)号：WO1983003065A1

公开(公告)日：1983-09-15

申请号：PCT/US1983000292

申请日：1983-03-04

Applicant: ECONOMICS LABORATORY, INC.

Inventor： ECONOMICS LABORATORY, INC. ,  PELLIGRINO, Peter, P.

IPC: B05D05/12

CPC classification number: H05K3/205 ,  H05K3/386 ,  H05K3/4626 ,  H05K2201/0195 ,  H05K2201/09118 ,  H05K2203/0152 ,  H05K2203/068 ,  H05K2203/0726

Abstract: Methods and apparatus (48) for providing fine line, high density multiple layer printed circuit board packages (44). In the method for fabricating multiple layer printed circuit board package (44), a printed circuit board (42) is formed having a conductive circuit pattern (18) embedded in and integral with an insulator material substrate (32), such that the surface of the conductive circuit pattern is exposed along one surface (34) of the substrate, and lays flush and coplanar therewith. At least two of said boards (42) are stacked with a layer of insulator material (44) interposed between each pair of adjacent boards (42). The entire assembly is heat-pressed together to form a homogeneous block of insulator material having conductive circuit patterns embedded and integrally molded therein.

Abstract translation: 用于提供细线，高密度多层印刷电路板封装（44）的方法和装置（48）。 在制造多层印刷电路板封装（44）的方法中，形成了具有嵌入绝缘体材料基板（32）并与绝缘体材料基板（32）成一体的导电电路图案（18）的印刷电路板（42） 导电电路图案沿着衬底的一个表面（34）暴露，并且与其平齐并共面。 至少两个所述板（42）堆叠有介于每对相邻板（42）之间的绝缘材料层（44）。 整个组件被热压在一起以形成绝缘体材料的均匀块，其具有嵌入并整体模制在其中的导电电路图案。

公开(公告)号：WO1982003802A1

公开(公告)日：1982-11-11

申请号：PCT/US1981000557

申请日：1981-04-28

Applicant: DIAMOND SHAMROCK CORP

Inventor： DIAMOND SHAMROCK CORP ,  BACZEK STANLEY K ,  MCCAIN HOWARD G

IPC: B05D05/12

CPC classification number: H01M8/1004 ,  C08J5/2237 ,  C08J2327/18 ,  C25B9/10 ,  H01M2/1613 ,  H01M2/162 ,  H01M2/1626 ,  H01M2/1673 ,  H01M8/1023 ,  H01M8/1039 ,  H01M8/106 ,  H01M8/1081 ,  H01M2300/0014 ,  Y02P70/56

Abstract: Normally solid copolymers of a fluorinated vinyl monomer and a perfluorinated vinyl compound having a carboxyl and/or sulfonyl group attached directly to the perfluorinated vinyl group or indirectly through an alkyl or ether linkage have been found to be soluble in low molecular weight polymers of perhalogenated alkyl ethers, low molecular weight polymers of perhalogenated alkyls and perfluoro kerosenes, each of said solvent materials having boiling points between about 200 C and 350 C. The copolymeric material dissolved in acordance with the instant invention can readily be resolidified by solvent removal and hydrolyzed or converted to the salt form to become a cation exchange material having an equivalent weight in the range of 1000 to 1600. Membrane coated cathodes can be formed using the dissolved copolymeric material and may be made by casting or coating a foraminous cathode followed by removal of the solvent to result in a continuous, pore-free coating of membrane on the cathode. Multiple coatings or other techniques can be used to build up the desired thickness of the membrane. Reinforced membrane may be produced by similar manufacturing techniques wherein the casting or coating of the membrane is upon a reinforcing backing fabric, which can be polytetrafluoroethylene mesh or the like is first wrapped around the foraminous cathode. The copolymeric material which is used in making the membrane coated cathode can be a single material or it can be of various equivalent weights, structures (carboxyl or sulfonyl, mixtures of same, or can be layers of the same or different materials).

Abstract translation: 已经发现通常将含氟乙烯基单体和具有羧基和/或磺酰基的全氟化乙烯基化合物的固体共聚物直接连接到全氟化乙烯基上或通过烷基或醚键间接连接，已经被发现可溶于低卤代烷基的低分子量聚合物 醚，全卤代烷基和全氟煤油的低分子量聚合物，每种所述溶剂材料的沸点在约200℃至350℃之间。 根据本发明溶解的共聚物质可以通过溶剂去除而容易地重新固化，并水解或转化为盐形式成为当量重量在1000至1600范围内的阳离子交换材料。膜涂覆的阴极可以使用 溶解的共聚物材料，并且可以通过浇铸或涂覆多孔阴极，然后除去溶剂来制造，从而在阴极上形成膜的连续，无孔的涂层。 可以使用多重涂层或其它技术来建立膜的所需厚度。 加强膜可以通过类似的制造技术制造，其中膜的浇铸或涂层在加强背衬织物上，其可以是聚四氟乙烯网或类似物首先缠绕在多孔阴极上。 用于制造膜涂覆阴极的共聚物可以是单一材料，也可以是各种等效的结构（羧基或磺酰基，相同的混合物，或可以是相同或不同材料的层）。

公开(公告)号：WO1998016326A1

公开(公告)日：1998-04-23

申请号：PCT/US1997018337

申请日：1997-10-09

Applicant: MAKO, Frederick, M. ,  SCHWARTZ, Ansel, M. ,  SILBERGLITT, Richard ,  PETER, William

Inventor： MAKO, Frederick, M. ,  SCHWARTZ, Ansel, M.

IPC: B05D05/12

CPC classification number: C23C28/044 ,  C23C14/0641 ,  C23C14/0647 ,  C23C14/0652 ,  H01J5/08

Abstract: A method of suppressing electrical breakdown on a surface of a substrate comprising the steps of applying a first coating layer (coating layer 2) on the surface of the substrate and applying at least one subsequent coating layer (coating layer 1) over the first coating layer.

Abstract translation: 一种抑制基板表面上的电击穿的方法，包括以下步骤：将第一涂层（涂层2）施加到基板的表面上，并将至少一个后续涂层（涂层1）涂覆在第一涂层 。

公开(公告)号：WO1998006510A1

公开(公告)日：1998-02-19

申请号：PCT/US1997013954

申请日：1997-08-12

Applicant: LIBBEY-OWENS-FORD CO. ,  PILKINGTON PLC

Inventor： LIBBEY-OWENS-FORD CO. ,  PILKINGTON PLC ,  McCURDY, Richard, J. ,  STRICKLER, David, A. ,  SANDERSON, Kevin, D.

IPC: B05D05/12

CPC classification number: C03C17/2453 ,  C03C17/245 ,  C03C2217/215 ,  C03C2217/231 ,  C03C2218/152 ,  C23C16/407

Abstract: The invention relates to the coating of flat glass with indium oxide. Indium oxide coatings, optionally doped, for example with tin, are produced in high yield by utilising a chemical vapour deposition process in which a gaseous mixture of an indium precursor compound and a source of oxygen is directed on to the hot glass surface; the indium precursor compound is preferably a dialkylindium compound (which may also be used without pre-mixing but with separate supply of the oxygen source to the glass surface). The processes of the invention are especially suitable for application of a doped indium oxide coating to a continuous ribbon of glass on the production line on which the glass is formed, for use, for example, in architectural glazing applications utilizing the low emissivity of the coating.

Abstract translation: 本发明涉及用氧化铟涂覆平板玻璃。 通过利用其中铟前体化合物和氧源的气体混合物指向热玻璃表面的化学气相沉积工艺以高产率生产任选掺杂的例如锡的氧化铟涂层; 铟前体化合物优选为二烷基鎓化合物（其也可以在不预混合的情况下使用，但是将氧源与玻璃表面单独供应）。 本发明的方法特别适合于在形成玻璃的生产线上将连续的玻璃带施加掺杂的氧化铟涂层，用于例如利用涂层的低发射率的建筑玻璃应用中 。