公开(公告)号：WO2022029418A1

公开(公告)日：2022-02-10

申请号：PCT/GB2021/051999

申请日：2021-08-02

Applicant: ARM LIMITED

Inventor： WILLIAMS, Michael John

IPC: G06F11/30 ,  G06F11/34 ,  G06F11/36 ,  G06F11/3466 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/3636 ,  G06F2201/81 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/88

Abstract: A data processing apparatus and a method for processing data are disclosed. The data processing apparatus comprises: processing circuitry to process instructions; and trace circuitry comprising: a trace buffer; write pointer storage to store a write pointer to indicate a current location in the trace buffer; and a call depth counter to indicate a number of events, wherein the trace circuitry is configured to generate trace data indicative of processing activities of the processing circuitry, and in response to a first event to: modify the call depth counter in a first direction, store first trace data indicative of the first event in the trace buffer at the current location, and modify the write pointer to point to a next location in the trace buffer; in response to a second event, when the call depth counter is not equal to a threshold call depth, to: modify the call depth counter in a second direction and modify the write pointer to point to a previous location in the trace buffer; and in response to the second event, when the call depth counter is equal to the threshold call depth, to store second trace data indicative of the second event in the trace buffer at the current location.

公开(公告)号：WO2021122920A1

公开(公告)日：2021-06-24

申请号：PCT/EP2020/086675

申请日：2020-12-17

Applicant: THALES

Inventor： BONNAFOUX, Luc ,  BENAMIRA, Adrien ,  DUPREZ, Adrien

IPC: G06F21/55 ,  G06F11/34 ,  G06F11/3409 ,  G06F11/3457 ,  G06F21/552 ,  G06F2201/88

Abstract: Procédé de contrôle d'un système électronique par compteurs de performance bas niveaux et comprenant au moins un ensemble d'applicatif(s) logiciels non maîtrisés s'exécutant sur un processeur et un dispositif de contrôle Procédé de contrôle du fonctionnement d'un système exécutant sur un processeur des applicatifs suite à des actions d'utilisateur et calculant des valeurs HPC, comprenant les étapes suivantes : - prédiction par un modèle algorithmique de valeurs prochaines de HPC en fonction de valeurs courantes de HPC et des actions; ledit modèle étant issu d'un processus d'apprentissage machine en fonction de données d'entrée d'apprentissage comprenant des valeurs successives HPC et des actions; - vérifier la conformité de fonctionnement du système par un module électronique de contrôle (17) en fonction de caractéristique(s) d'une première déviation calculée entre des valeurs HPC calculées et des valeurs HPC prédites par le premier modèle algorithmique; et déclenchement d'une alerte par ledit module électronique de contrôle dès détection d'une non-conformité.

公开(公告)号：WO2022109142A2

公开(公告)日：2022-05-27

申请号：PCT/US2021/059901

申请日：2021-11-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BONITZ, Rainer F. ,  HUO, Binbin

IPC: G06F11/14 ,  G06F11/20 ,  G06F11/22 ,  G06F11/30 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/1428 ,  G06F11/1443 ,  G06F11/2007 ,  G06F11/221 ,  G06F11/26 ,  G06F11/302 ,  G06F11/3027 ,  G06F11/3034 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: A computing system can comprise a processing resource and a memory device coupled together via a first transmission link. The processing resource can be configured to test the first transmission link in response to the memory device failing to execute a command by sending the command to the memory device again for retry and monitoring the first transmission link for signals that indicate whether the command was executed by the memory device.

公开(公告)号：WO2021229291A1

公开(公告)日：2021-11-18

申请号：PCT/IB2020/062561

申请日：2020-12-30

Applicant: COUPANG CORP.

Inventor： KIM, Kyung Jun ,  KIM, Sung Ho

IPC: G06F11/36 ,  G06F9/50 ,  G06F9/455 ,  G06F11/1629 ,  G06F11/301 ,  G06F11/3409 ,  G06F11/3428 ,  G06F11/3457 ,  G06F11/3684 ,  G06F11/3688 ,  G06F11/3692 ,  G06F2009/45591 ,  G06F2201/81 ,  G06F2201/815 ,  G06F2201/88 ,  G06F9/45504 ,  G06F9/45558

Abstract: Methods and systems for test deployment of computational code on virtual servers are disclosed. In one embodiment, an exemplary method comprises receiving test computational code programmed to provide resources; selecting a test virtual server from a plurality of virtual servers; uploading the test computational code to the test virtual server; initializing the test computational code on the test virtual server; receiving computational performance measurements of the test virtual server and a remainder of the plurality of virtual servers; calculating a test score of the test virtual server based on the received computational performance measurements; and stopping the test computational code if the test score is outside a set range.

公开(公告)号：WO2021122066A1

公开(公告)日：2021-06-24

申请号：PCT/EP2020/084687

申请日：2020-12-04

Applicant: COMMSOLID GMBH

Inventor： JAKSCHIK, Daniel

IPC: G06F13/42 ,  G06F11/30 ,  G06F11/36 ,  G06F11/3024 ,  G06F11/3065 ,  G06F11/3068 ,  G06F11/348 ,  G06F13/4208 ,  G06F2201/88

Abstract: The invention discloses a trace handler module system and a method for generating a trace data stream out of trace messages using a minimum set of processor instructions by using said trace handler module system. The object of the present invention to provide an apparatus and a method that are able to handle trace messages that are extracted out of the firmware flow of the processor consuming minimal controller bandwidth and without introducing runtime variations will be solved by a trace handler module system which is configured to take over a trace message representing an internal state of a firmware running on a processor of a SoC via a chip-internal bus system, wherein the trace message is carried by a bus data signal which is exchanged between a bus master and a bus slave over the chip-internal bus system and a bus address-signal is used to encode additional trace meta data of the trace message, wherein the trace handler module system comprises the bus slave configured to convert specific bus protocol data to strobe-based protocol data, an input logic configured to add timestamps, to do filtering and channel allocation of the converted data from the bus slave, a first-in-first-out (FIFO) shift register configured to decouple a bus transfer speed from a trace data stream speed and to output a FIFO data format, and an output logic configured to convert the FIFO data format to a trace data stream format representing the trace message to reconstruct a system behavior issued by the processor.