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    AN ARRAY AND CMOS ARCHITECTURE FOR 3D PHASE CHANGE MEMORY WITH HIGHER ARRAY EFFICIENCY
    1.
    发明申请
    AN ARRAY AND CMOS ARCHITECTURE FOR 3D PHASE CHANGE MEMORY WITH HIGHER ARRAY EFFICIENCY 审中-公开

    公开(公告)号：WO2021243641A1

    公开(公告)日：2021-12-09

    申请号：PCT/CN2020/094346

    申请日：2020-06-04

    Applicant: YANGTZE ADVANCED MEMORY INDUSTRIAL INNOVATION CENTER CO., LTD

    Inventor： LIU, Jun

    IPC: G11C13/00 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  H01L27/2481

    Abstract: A three-dimensional memory architecture including a top cell array of memory cells, a bottom cell array of memory cells, a plurality of word lines coupled to the arrays, and a plurality of word line decoders coupled to the word lines and operable to selectively activate the word lines. The plurality of word line decoders extend from a first edge of the bottom cell array and from a second edge of the bottom cell array, the second edge being opposite the first edge, wherein the plurality of word line decoders include a first portion of word line decoders and a second portion of word line decoders, and wherein the first portion of word line decoders is shifted relative to the second portion of the word line decoders along a direction parallel, or substantially parallel, to the first edge and second edge.

    PHASE CHANGE DEVICE
    2.
    发明申请
    PHASE CHANGE DEVICE 审中-公开

    公开(公告)号：WO2021254241A1

    公开(公告)日：2021-12-23

    申请号：PCT/CN2021/099344

    申请日：2021-06-10

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM (CHINA) CO., LIMITED

    Inventor： LI, Ning ,  SADANA, Devendra, K.

    IPC: H01L45/00 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/50 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/128 ,  H01L45/14 ,  H01L45/1608

    Abstract: A phase change device (PCD) has a first and second semiconductor layer. The first semiconductor layer made of a first semiconductor material and has a first semiconductor thickness, a first interface surface, and a first electrode surface. The first interface surface and first electrode surface are on opposite sides of the first semiconductor layer. The first semiconductor material can transition between a first amorphous state and a first crystalline state at one or more first conditions. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness, a second interface surface, and a second electrode surface. The second interface surface and second electrode surface are on opposite sides of the second semiconductor layer. The first interface surface and the second interface surface are in electrical, physical, and chemical contact with one another at an interface. The second semiconductor material can transition between a second amorphous state and a second crystalline state at one or more second conditions. A first electrode in physical and electrical contact with the first electrode surface of the first semiconductor layer and a second electrode in physical and electrical contact with the second electrode surface of the second semiconductor layer. The first conditions and second conditions are different. Therefore, the first and second semiconductor materials can be in different amorphous and/or crystalline states. The layers can have split amorphous/crystalline states. By controlling how the layers are split, the PCD can be in different resistive states.

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