公开(公告)号：WO99014674A1

公开(公告)日：1999-03-25

申请号：PCT/DE1998/002250

申请日：1998-08-05

IPC: G11C29/00 ,  G11C29/28 ,  G11C29/34 ,  G06F11/20

CPC classification number: G11C29/789 ,  G11C29/28 ,  G11C29/34

Abstract: The invention relates to a dynamic memory having memory cells which are assembled in blocks (B) and can be selected through bit lines (BL) and word lines (WL). The blocks are assembled in at least one group of blocks (BG). In a first operating mode, no more than one of the word lines (WL) is simultaneously selected for each group of blocks (BG). In a second operating mode, more than one word line (WL) is simultaneously selected for each group of blocks (BG).

Abstract translation: 动态存储器经由位线（BL）和字线（WL）上可选择的分配块（B）组合的存储器单元。 的嵌段（B）被结合以形成至少一个块组（BG）。 在字线（WL）的最每一个块组（BG）的第一模式在同一时间被选择。 在第二模式中，每个块组（BG）的字线中的多于一个（WL）同时被选择。

公开(公告)号：WO2010129127A3

公开(公告)日：2011-01-20

申请号：PCT/US2010030167

申请日：2010-04-07

Applicant: SYNOPSYS INC ,  NICOLAIDIS MICHAEL ,  BOUTOBZA SLIMANE

Inventor： NICOLAIDIS MICHAEL ,  BOUTOBZA SLIMANE

IPC: G11C29/28 ,  G11C29/12 ,  G11C29/34

CPC classification number: G11C29/16 ,  G11C8/16 ,  G11C29/56

Abstract: One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access operations are performed. During operation, the system can receive an instruction sequence, which implements a new test procedure for testing the memory device, while the memory device is being tested. Furthermore, the system can implement a built-in self-test (BIST) solution for testing any multi-port memory device, and can generate tests targeted to a specific memory design based in part on information from the instruction sequence.

Abstract translation: 一个实施例提供了一种运行时可编程系统，其包括用于测试多端口存储器设备以检测多端口存储器故障的方法和装置，以及当访问存储器的单个端口时可被激活的典型单端口存储器故障 设备。 更具体地说，该系统包括多个机构，其可被配置为激活和检测在执行两个同时存储器访问操作时影响存储器设备的任何现实故障。 在操作期间，系统可以接收指令序列，该指令序列在测试存储器件的同时实现用于测试存储器件的新测试程序。 此外，系统可以实现内置的自检（BIST）解决方案，用于测试任何多端口存储设备，并且可以部分地基于指令序列的信息，生成针对特定存储器设计的测试。

公开(公告)号：WO2010129127A2

公开(公告)日：2010-11-11

申请号：PCT/US2010/030167

申请日：2010-04-07

Applicant: SYNOPSYS, INC. ,  NICOLAIDIS, Michael ,  BOUTOBZA, Slimane

Inventor： NICOLAIDIS, Michael ,  BOUTOBZA, Slimane

IPC: G11C29/28 ,  G11C29/34 ,  G11C29/12

CPC classification number: G11C29/16 ,  G11C8/16 ,  G11C29/56

Abstract: One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access operations are performed. During operation, the system can receive an instruction sequence, which implements a new test procedure for testing the memory device, while the memory device is being tested. Furthermore, the system can implement a built-in self-test (BIST) solution for testing any multi-port memory device, and can generate tests targeted to a specific memory design based in part on information from the instruction sequence.

Abstract translation: 一个实施例提供了一种运行时可编程系统，其包括用于测试多端口存储器设备以检测多端口存储器故障的方法和装置，以及当访问存储器的单个端口时可被激活的典型单端口存储器故障 设备。 更具体地说，该系统包括多个机构，其可被配置为激活和检测在执行两个同时存储器访问操作时影响存储器设备的任何现实故障。 在操作期间，系统可以接收指令序列，该指令序列在测试存储器件的同时实现用于测试存储器件的新测试程序。 此外，系统可以实现内置的自检（BIST）解决方案，用于测试任何多端口存储设备，并且可以部分地基于指令序列的信息，生成针对特定存储器设计的测试。