公开(公告)号：WO0054410A8

公开(公告)日：2001-06-14

申请号：PCT/FR0000573

申请日：2000-03-08

Applicant: IROC TECHNOLOGIES ,  NICOLAIDIS MICHAEL

Inventor： NICOLAIDIS MICHAEL

IPC: G06F12/16 ,  G06F11/10 ,  H03K19/003 ,  H03K19/23 ,  H03M13/05 ,  H03M13/43 ,  G06F11/18 ,  H03K3/013

CPC classification number: G06F11/1497 ,  G06F11/10 ,  H03K19/00338

Abstract: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10) having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control is incorrect.

Abstract translation: 本发明涉及一种防止瞬时扰动的电路，包括具有至少一个输出（A）的组合逻辑电路（10）; 产生用于所述输出的错误控制代码的电路（20）和设置在所述输出端的存储元件（24），所述存储元件（24）由所述电路控制，所述电路在所述控制代码正确时产生要透明的控制代码，并且当 控制不正确。

公开(公告)号：WO03032160A2

公开(公告)日：2003-04-17

申请号：PCT/FR0203484

申请日：2002-10-11

Applicant: IROC TECHNOLOGIES ,  NICOLAIDIS MICHAEL

Inventor： NICOLAIDIS MICHAEL

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G11C7/02 ,  G11C7/04

CPC classification number: G06F11/141 ,  G06F11/1016

Abstract: The invention concerns a digital circuit architecture comprising combinational circuits (10, 12), short-term memory circuits (11) not capable of storing data for more than k operating cycles, long-term memory circuits (13) capable of storing data for more than k operating cycles of the circuit. Systems for protection against different perturbations are used for the different types of circuits and based on the functionality of said circuits.

Abstract translation: 本发明涉及包括组合电路（10,12），不能存储超过k个操作周期的数据的短期存储器电路（11）的数字电路架构，能够存储更多数据的长期存储器电路（13） 比电路的k个工作周期。 用于不同扰动的保护系统用于不同类型的电路并且基于所述电路的功能。

公开(公告)号：WO2010129127A3

公开(公告)日：2011-01-20

申请号：PCT/US2010030167

申请日：2010-04-07

Applicant: SYNOPSYS INC ,  NICOLAIDIS MICHAEL ,  BOUTOBZA SLIMANE

Inventor： NICOLAIDIS MICHAEL ,  BOUTOBZA SLIMANE

IPC: G11C29/28 ,  G11C29/12 ,  G11C29/34

CPC classification number: G11C29/16 ,  G11C8/16 ,  G11C29/56

Abstract: One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access operations are performed. During operation, the system can receive an instruction sequence, which implements a new test procedure for testing the memory device, while the memory device is being tested. Furthermore, the system can implement a built-in self-test (BIST) solution for testing any multi-port memory device, and can generate tests targeted to a specific memory design based in part on information from the instruction sequence.

Abstract translation: 一个实施例提供了一种运行时可编程系统，其包括用于测试多端口存储器设备以检测多端口存储器故障的方法和装置，以及当访问存储器的单个端口时可被激活的典型单端口存储器故障 设备。 更具体地说，该系统包括多个机构，其可被配置为激活和检测在执行两个同时存储器访问操作时影响存储器设备的任何现实故障。 在操作期间，系统可以接收指令序列，该指令序列在测试存储器件的同时实现用于测试存储器件的新测试程序。 此外，系统可以实现内置的自检（BIST）解决方案，用于测试任何多端口存储设备，并且可以部分地基于指令序列的信息，生成针对特定存储器设计的测试。

公开(公告)号：WO2010129127A2

公开(公告)日：2010-11-11

申请号：PCT/US2010/030167

申请日：2010-04-07

Applicant: SYNOPSYS, INC. ,  NICOLAIDIS, Michael ,  BOUTOBZA, Slimane

Inventor： NICOLAIDIS, Michael ,  BOUTOBZA, Slimane

IPC: G11C29/28 ,  G11C29/34 ,  G11C29/12

CPC classification number: G11C29/16 ,  G11C8/16 ,  G11C29/56

Abstract: One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access operations are performed. During operation, the system can receive an instruction sequence, which implements a new test procedure for testing the memory device, while the memory device is being tested. Furthermore, the system can implement a built-in self-test (BIST) solution for testing any multi-port memory device, and can generate tests targeted to a specific memory design based in part on information from the instruction sequence.

Abstract translation: 一个实施例提供了一种运行时可编程系统，其包括用于测试多端口存储器设备以检测多端口存储器故障的方法和装置，以及当访问存储器的单个端口时可被激活的典型单端口存储器故障 设备。 更具体地说，该系统包括多个机构，其可被配置为激活和检测在执行两个同时存储器访问操作时影响存储器设备的任何现实故障。 在操作期间，系统可以接收指令序列，该指令序列在测试存储器件的同时实现用于测试存储器件的新测试程序。 此外，系统可以实现内置的自检（BIST）解决方案，用于测试任何多端口存储设备，并且可以部分地基于指令序列的信息，生成针对特定存储器设计的测试。

公开(公告)号：WO2006134308A3

公开(公告)日：2007-03-01

申请号：PCT/FR2006050567

申请日：2006-06-16

Applicant: IROC TECHNOLOGIES ,  NICOLAIDIS MICHAEL

Inventor： NICOLAIDIS MICHAEL

IPC: G11C11/412 ,  G11C5/00 ,  G11C29/42

CPC classification number: G11C5/005 ,  G11C11/4125

Abstract: The invention concerns an integrated circuit chip comprising a large number of semiconductor components having parasite components through which a short circuit between the supply voltage and the circuit ground is likely to be triggered, said semiconductor components being distributed into elementary blocks, each elementary block being independently connected to supply or ground lines of the main supply network of the integrated circuit by a current limiting device capable of checking a short circuit triggered in the block concerned, and each block being dimensioned such that software errors likely to occur in said block are capable of being corrected by means of error correction.

Abstract translation: 本发明涉及一种集成电路芯片，其包括具有寄生元件的大量半导体元件，通过该寄生电子元件可以触发电源电压和电路地之间的短路，所述半导体元件被分配到基本块中，每个基本块是独立的 通过能够检查相关块中触发的短路的限流装置连接到集成电路的主供电网络的供电或接地线，并且每个块的尺寸使得所述块中可能发生的软件错误能够 通过纠错纠正。

公开(公告)号：WO1993018457A1

公开(公告)日：1993-09-16

申请号：PCT/GR1993000005

申请日：1993-03-05

Applicant: SOFIA KOLONI LTD. ,  NICOLAIDIS, Michael

Inventor： SOFIA KOLONI LTD.

IPC: G06F11/26

CPC classification number: G01R31/318527 ,  G01R31/318533 ,  G01R31/318536 ,  G06F11/221 ,  G06F11/2273 ,  G06F11/27 ,  G06F11/2733 ,  G06F2201/83 ,  G11C29/32 ,  G11C29/40

Abstract: A technique for transparent testing of integrated circuits has been described. It allows to test the integrated circuits without losing the applications' execution context. The technique considers two kinds of blocks, combinational and sequential blocks on the one hand and RAMs and register files on the other hand. For the first kind of blocks we propose a save, test and restore technique. It takes advantage from a circular scan path implementation and consists on shifting (via the scan path) the contents of various registers until the data inputs of a RAM, it saves the registers' contents in the RAM, performs the test session, loads back the saved data to the scan path and shifts them until the corresponding registers. For the second kind of blocks we propose a transparent test technique allowing to test the RAMs without destroying their initial contents. To do that we propose a technique allowing to derive RAM transparent test processes. These thest processes can be implemented by means of BIST techniques, or by means of scan path techniques. The transparent test processes are composed by a signature prediction or a signature initialisation process and a basic transparent test process. The signature prediction test process is obtained from the basic transparent test process by removing all the write operations. The read operations such that the read data are not injected to the output compaction scheme can also be removed. This technique avoids fault masking due to errors produced during both the signature prediction test process and the basic transparent test process. The basic transparent test process can be obtained from any standard (i.e. non transparent) test process by using several transformation steps. These transformation steps are such that for all the RAM fault models verifying some symmetric property, the basic transparent test process offers the same fault coverage as the standard test process. This property is verified by nearly all the RAM fault models. The signature initialisation process is derived from the signature prediction process by reversing its ordering. When this process is used it is coupled with some new data compactors named Up/Down data compactors. These compactors allow for the whole process (i.e. signature initialisation process plus basic transparent test process) to give a predicted signature.

Abstract translation: 已经描述了用于集成电路的透明测试的技术。 它允许测试集成电路，而不会丢失应用程序的执行上下文。 该技术一方面考虑两种块，组合和顺序块，另一方面考虑RAM和寄存器文件。 对于第一类块，我们提出了一种保存，测试和恢复技术。 它采用循环扫描路径实现，并且包括通过移动（通过扫描路径）各种寄存器的内容，直到RAM的数据输入，它将寄存器的内容保存在RAM中，执行测试会话，加载回 将数据保存到扫描路径，并将其移动到相应的寄存器。 对于第二种类型的块，我们提出了一种透明的测试技术，允许测试RAM而不会破坏它们的初始内容。 为此，我们提出一种允许导出RAM透明测试过程的技术。 这些第一个过程可以通过BIST技术或通过扫描路径技术来实现。 透明测试过程由签名预测或签名初始化过程和基本的透明测试过程组成。 通过删除所有写入操作，从基本透明测试过程获得签名预测测试过程。 读取操作使得读取的数据不被注入到输出压缩方案中也可以被去除。 该技术避免了在签名预测测试过程和基本透明测试过程期间产生的错误导致的故障屏蔽。 可以通过使用几个变换步骤从任何标准（即非透明）测试过程获得基本的透明测试过程。 这些转换步骤对于验证某些对称属性的所有RAM故障模型，基本的透明测试过程提供与标准测试过程相同的故障覆盖。 该属性几乎全部由RAM故障模型进行验证。 签名初始化过程通过反转其排序从签名预测过程中导出。 当使用此过程时，它与一些名为Up / Down数据压缩机的新型数据压缩机相结合。 这些压实机允许整个过程（即签名初始化过程加上基本的透明测试过程）来给出预测的签名。

公开(公告)号：WO2003032160A3

公开(公告)日：2003-04-17

申请号：PCT/FR2002/003484

申请日：2002-10-11

Applicant: IROC TECHNOLOGIES ,  NICOLAIDIS, Michael

Inventor： NICOLAIDIS, Michael

IPC: G06F11/10

Abstract: L'invention concerne une architecture de circuit numérique comprenant des circuits combinatoires (10, 12), des circuits de mémoire de courte durée (11) non suseptibles de stocker des données pendant plus de k cycles de fonctionnement, des circuits de mémoire de longue durée (13) susceptibles de stocker des données pendant plus de k cycles de fonctionnement du circuit. Des systèmes de protection contre les perturbations distincts sont utilisées pour les différents types de circuits et selon la fonctionnalité de ces circuits.

公开(公告)号：WO1995034858A1

公开(公告)日：1995-12-21

申请号：PCT/FR1995000767

申请日：1995-06-12

Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  NICOLAIDIS, Michael ,  VARGAS, Fabian

Inventor： CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE

IPC: G06F11/10

CPC classification number: G06F11/0754 ,  G06F11/1008 ,  G11C29/50

Abstract: Static memory comprising memory cells (MC) arranged in rows and columns, each row of cells constituting of at least one word and a corresponding error control code. Each cell column comprises at least one specific power line (Vcc', GND') connected to a general power line (Vcc', GND') of the memory through a current detector (10, 12). Each detector activates an error signal if the associated specific supply line current exceeds a predetermined threshhold.

Abstract translation: 静态存储器包括排列成行和列的存储单元（MC），每行单元构成至少一个单词和对应的错误控制代码。 每个单元列包括通过电流检测器（10,12）连接到存储器的一般电力线（Vcc'，GND'）的至少一个特定电力线（Vcc'，GND'）。 如果相关的特定电源线电流超过预定阈值，则每个检测器激活误差信号。

公开(公告)号：WO1995006908A1

公开(公告)日：1995-03-09

申请号：PCT/GR1994000021

申请日：1994-09-02

Applicant: SOFIA KOLONI LTD. ,  NICOLAIDIS, Michael

Inventor： SOFIA KOLONI LTD.

IPC: G06F11/08

CPC classification number: G06F11/0796 ,  G06F11/085 ,  H03K19/0075

Abstract: The present invention relates to a fail-safe control interface including branches for providing signals having a safe state or a non-safe state. Each branch comprises inputs for receiving at least two binary control signals (Si, Si*); a source of a non-safe state (Fe) connectable through a basic chain of elements (14, 15) to an output (Oi) when the control signals realize a predetermined combination; a concurrent checker (17) providing an error detection signal (g1, g2) if the inputs of a pair of its inputs are at predetermined states; and means (14*) for providing a first input of said pair of inputs with a signal corresponding to the state of said output and the second input of said pair of inputs with a signal corresponding to the output of a duplicate chain of the basic chain, this duplicate chain reacting like the basic chain in response to the control signals.

Abstract translation: 本发明涉及包括用于提供具有安全状态或非安全状态的信号的分支的故障安全控制接口。 每个分支包括用于接收至少两个二进制控制信号（Si，Si *）的输入; 当控制信号实现预定组合时，通过元件（14,15）的基本链可连接到输出（Oi）的非安全状态（Fe）源; 如果一对其输入的输入处于预定状态，则提供错误检测信号（g1，g2）的并行检查器（17） 以及用于通过对应于所述基本链的重复链的输出的信号来提供所述输入对的第一输入与所述输出的状态和所述输入对的所述第二输入的信号的装置（14 *） ，这个重复的链反应如基本链响应控制信号。

公开(公告)号：WO1993021576A1

公开(公告)日：1993-10-28

申请号：PCT/GR1993000007

申请日：1993-04-14

Applicant: SOFIA KOLONI LTD. ,  NICOLAIDIS, Michael

Inventor： SOFIA KOLONI LTD.

IPC: G06F07/49

CPC classification number: G06F11/085 ,  G06F7/00 ,  G06F11/10

Abstract: Method of self-checking arithmetic units and data paths using the double rail code for the arithmetic operators and a parity code for the other blocks. The method uses a single block for the generation of both codes, thus avoiding the need of code translators. The ripple-carry adders, ALU's, multiply and divide arrays are implemented with DCVS or static differential gates, to avoid overhead (Output Checking/Parity Generation Scheme). When the adders or ALU's are of a certain length, the schemes used are the Carry and Output Checking/Parity Generation and Carry Checking/Parity Prediction.

Abstract translation: 使用算术运算符的双轨代码进行自检算术单元和数据路径的方法以及其他块的奇偶校验码。 该方法使用单个块来生成两个代码，从而避免了代码转换器的需要。 纹波携带加法器，ALU，乘法和除法阵列由DCVS或静态差分门实现，以避免开销（输出检查/奇偶校验生成方案）。 当加法器或ALU具有一定长度时，所使用的方案是进位和输出检查/奇偶校验生成和进位检查/奇偶校验预测。