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    ELECTRONIC DEVICE, PACKAGE AND SEMICONDUCTOR CHIP THEREFORE
    3.
    发明申请
    ELECTRONIC DEVICE, PACKAGE AND SEMICONDUCTOR CHIP THEREFORE 审中-公开

    公开(公告)号：WO2022043033A1

    公开(公告)日：2022-03-03

    申请号：PCT/EP2021/072081

    申请日：2021-08-06

    Applicant: HITACHI ENERGY SWITZERLAND AG [CH]/[CH]

    Inventor： STIASNY, Thomas ,  WIKSTROEM, Tobias

    IPC: H01L21/603 ,  H01L23/051 ,  H01L25/10 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/04 ,  H01L2224/04042 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/48091 ,  H01L2224/73201 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/72 ,  H01L24/73 ,  H01L25/117

    Abstract: An electronic device (1) comprises a semiconductor chip (2) having an electrical contact metallization (3), and a package (4) having an electrical contact disc (5). The electrical contact metallization (3) and the electrical contact disc (5) are in direct contact on a contact face (45) so that the semiconductor chip (2) is electrically connected with the package (4). At the contact face (45), at least one of the electrical contact metallization (3) and the electrical contact disc (5) comprises a geometric structuring (6) (a surface pattern) fashioned as at least one recessed area. A mean roughness of a top face (50) of the electrical contact disc (5) facing the electrical contact metallization (3) may be between 0.2 pm and 1 pm, wherein, because of the mean roughness, the top face (50) is configured to penetrate an oxide layer (31) of the electrical contact metallization (3) at the contact face (45) (e.g., native oxide on an aluminum metallization (3) ). The electrical contact metallization (3) may be of multilayer fashion and comprise at least one interrupted sub-layer (33) and at least one continuous sub-layer (34), the continuous sub-layer (34) being located at the contact face (45), wherein the at least one interrupted sub-layer (33) and the at least one continuous sub-layer (34) may be of the same material or of different materials, but have different thicknesses. All of the electrical contact metallization (3) and/or of the electrical contact disc (5) may be configured to be on the same electric potential. The geometric structuring (6) may consist of or comprise at least one of the following shapes: circle, spiral, rectangle, triangle, hexagon, honeycomb and may comprise interruptions. The semiconductor chip (2) may comprise a further electrical contact metallization (7) having an even and smooth further contact face (70), wherein, seen in top view, an overall size of the further contact face (70) is smaller than that of the electrical contact metallization (3) by at least a factor of 1.5 and by at most a factor of 5, and wherein, because of the geometric structuring (6), at the contact face (45) an effective size of the electrical contact metallization (3) is the same as the overall size of the further contact face (70), with a tolerance of at most a factor of 1.2, wherein the electrical contact metallization (3) and the further electrical contact metallization (7) may be located at opposite main sides of the semiconductor chip (2) and the semiconductor chip (2) is configured to be electrically contacted with a contact force of at least 0.3 kN/cm and of at most 2 kN/cm. The package (4) may comprise an electrically insulating jacket (41) and an electrical metal contact plate (42), wherein the semiconductor chip (2) and the electrical contact disc (5) as well as the metal plate (42) are arranged in the jacket (41) and are aligned in parallel with each other, wherein, seen in top view onto the contact face (45), sizes of the semiconductor chip (2) and the electrical contact disc (5) differ from each other by at most a factor of 1.3, and wherein the electrical contact disc (5) is located between the semiconductor chip (2) and the contact plate (42). The semiconductor chip (2), the electrical contact disc (5) and the optional contact plate (42) can be of circular shape seen in top view. The electronic device (1) may be a press pack power semiconductor device. The pressure at a given contact force is increased in the electronic device (1) by reducing the overall contact area, that is, a contact face (45) between the electrical contact metallization (3) of the semiconductor chip (2) and the electrical contact disc (5) of the package (4), to form a reliable and stable dry interface electric contact and avoid 'too low pressure1 effects, for example: for an anode side metallization of an IGCT or of an GTO, as the clamping force is typically limited for by the mechanical stability of the cathode side metallization which is in total significantly lower in contact area and more fragile due to the segmentation of a high metal stack; for a metallization of a free-floating side of a bonded diode used at low clamping forces, for example, when clamped with an IGCT - for a free-floating anode side, the probability of electromigration may be higher; or for an anode and cathode side metallization of a free-floating diode or of a free-floating plus diode clamped at relatively low pressures.

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