公开(公告)号：WO2021259477A1

公开(公告)日：2021-12-30

申请号：PCT/EP2020/067772

申请日：2020-06-25

申请人： HUAWEI TECHNOLOGIES CO., LTD. ,  BADAROGLU, Mustafa

发明人： BADAROGLU, Mustafa

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L2224/03845 ,  H01L2224/04105 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80006 ,  H01L2224/80013 ,  H01L2224/80047 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06593 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50

摘要： A method of stacking semiconductor components, to obtain a semiconductor wafer assembly, and for forming a semiconductor die assembly therefrom, is provided. The method comprises providing a first wafer comprising at least a first and a second die in a first and a second position, respectively; providing at least a third and a fourth die, to be stacked on the first and the second die, respectively; placing the third and fourth die on a carrier wafer in positions matching at least a part of the first and second position, respectively; applying insulating material on the carrier wafer outside of the third and the fourth dies; and placing the carrier wafer on the first wafer to obtain a first die stack of the first and third dies and a second die stack of the second and fourth dies, causing bonding of the first and third dies and the second and fourth dies, respectively.

公开(公告)号：WO2022212596A1

公开(公告)日：2022-10-06

申请号：PCT/US2022/022677

申请日：2022-03-30

申请人： INVENSAS BONDING TECHNOLOGIES, INC.

发明人： UZOH, Cyprian, Emeka ,  WORKMAN, Thomas

IPC分类号： H01L23/00 ,  H01L2224/03009 ,  H01L2224/038 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/80004 ,  H01L2224/80009 ,  H01L2224/80031 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/94 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L2924/095

摘要： Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.

公开(公告)号：WO2022182461A2

公开(公告)日：2022-09-01

申请号：PCT/US2022/013697

申请日：2022-01-25

申请人： QUALCOMM INCORPORATED

发明人： HU, Wei ,  HE, Dongming ,  YIN, Wen ,  GUAN, Zhe ,  ZHAO, Lily

IPC分类号： H01L23/485 ,  H01L21/60 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11622 ,  H01L2224/118 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13171 ,  H01L2224/13565 ,  H01L2224/13584 ,  H01L2224/13624 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13686 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2924/3651 ,  H01L2924/381 ,  H01L2924/3841

摘要： An IC package (900A-E) includes a substrate (920) and an integrated circuit (IC) structure comprising a die (410, 510, 610, 710, 810) (e.g., a flip-chip (FC) die) and one or more die interconnects (430) to electrically couple the die (410, 510, 610, 710, 810) to the substrate (920). The die interconnect (430) includes a pillar (440, 540, 640, 740, 840), a wetting barrier (460, 560, 660, 760, 860) on the pillar (440, 540, 640, 740, 840), and a solder cap (450, 550, 650, 750, 850) on the wetting barrier (460, 560, 660, 760, 860). The wetting barrier (460, 560, 660, 760, 860) is wider than the pillar (440, 540, 640, 740, 840), such that, during solder reflow, solder wetting of sidewall of the pillar (440, 540, 640, 740, 840) is minimised or prevented altogether. The width of the wetting barrier (460, 560, 660, 760, 860) may be greater than a width of the solder cap (450, 550, 650, 750, 850). The die interconnect (430) may also include a low wetting layer (470, 570, 770, 870) formed on at least a portion of a surface of the wetting barrier (460, 560, 760, 860) not covered by the pillar (440, 540, 740, 840), which can further mitigate solder wetting problems. The low wetting layer (470, 570, 770, 870) may have a lower solderability than the pillar (440, 540, 740, 840), for example, it may be made from metals such as Ni, Al, Cr, etc. The pillar (440, 540, 740) and the wetting barrier (460, 560, 760) may be formed from a same conductive material (e.g., Cu). Alternatively, the pillar (440) and the wetting barrier (460) may be formed from different conductive materials, with the material of the wetting barrier (460) (e.g., Ni) selected so as to also provide a chemical barrier to solder wetting on sidewalls of the pillar (440) (e.g., Cu). The IC structure may further comprise a contact layer (e.g., Ni) (780) in between the wetting barrier (760) and the solder cap (750). Alternatively, the low wetting layer (570, 870) may also be formed in between the wetting barrier (560, 860) and the solder cap (550, 850), wherein the pillar (840) may further be a first pillar, the IC structure further comprising a second pillar (890) (e.g., Cu) on the low wetting layer (870) and a contact layer (e.g., Ni) (880) between the second pillar (890) and the solder cap (850).

公开(公告)号：WO2022046482A2

公开(公告)日：2022-03-03

申请号：PCT/US2021/046455

申请日：2021-08-18

申请人： MICRON TECHNOLOGY, INC.

发明人： KIRBY, Kyle K. ,  PAREKH, Kunal R.

IPC分类号： H01L23/485 ,  H01L27/11573 ,  H01L21/60 ,  H01L21/683 ,  H01L21/50 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/08058 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/13111 ,  H01L2224/80006 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/11582

摘要： Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

公开(公告)号：WO2022005669A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/034862

申请日：2021-05-28

申请人： QUALCOMM INCORPORATED

发明人： SUN, Yangyang ,  HE, Dongming ,  ZHAO, Lily

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05147 ,  H01L2224/05555 ,  H01L2224/0603 ,  H01L2224/06163 ,  H01L2224/06164 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13211 ,  H01L2224/13239 ,  H01L2224/1403 ,  H01L2224/14164 ,  H01L2224/14505 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2924/014

摘要： Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.

公开(公告)号：WO2022043033A1

公开(公告)日：2022-03-03

申请号：PCT/EP2021/072081

申请日：2021-08-06

申请人： HITACHI ENERGY SWITZERLAND AG [CH]/[CH]

发明人： STIASNY, Thomas ,  WIKSTROEM, Tobias

IPC分类号： H01L21/603 ,  H01L23/051 ,  H01L25/10 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/04 ,  H01L2224/04042 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/48091 ,  H01L2224/73201 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/72 ,  H01L24/73 ,  H01L25/117

摘要： An electronic device (1) comprises a semiconductor chip (2) having an electrical contact metallization (3), and a package (4) having an electrical contact disc (5). The electrical contact metallization (3) and the electrical contact disc (5) are in direct contact on a contact face (45) so that the semiconductor chip (2) is electrically connected with the package (4). At the contact face (45), at least one of the electrical contact metallization (3) and the electrical contact disc (5) comprises a geometric structuring (6) (a surface pattern) fashioned as at least one recessed area. A mean roughness of a top face (50) of the electrical contact disc (5) facing the electrical contact metallization (3) may be between 0.2 pm and 1 pm, wherein, because of the mean roughness, the top face (50) is configured to penetrate an oxide layer (31) of the electrical contact metallization (3) at the contact face (45) (e.g., native oxide on an aluminum metallization (3) ). The electrical contact metallization (3) may be of multilayer fashion and comprise at least one interrupted sub-layer (33) and at least one continuous sub-layer (34), the continuous sub-layer (34) being located at the contact face (45), wherein the at least one interrupted sub-layer (33) and the at least one continuous sub-layer (34) may be of the same material or of different materials, but have different thicknesses. All of the electrical contact metallization (3) and/or of the electrical contact disc (5) may be configured to be on the same electric potential. The geometric structuring (6) may consist of or comprise at least one of the following shapes: circle, spiral, rectangle, triangle, hexagon, honeycomb and may comprise interruptions. The semiconductor chip (2) may comprise a further electrical contact metallization (7) having an even and smooth further contact face (70), wherein, seen in top view, an overall size of the further contact face (70) is smaller than that of the electrical contact metallization (3) by at least a factor of 1.5 and by at most a factor of 5, and wherein, because of the geometric structuring (6), at the contact face (45) an effective size of the electrical contact metallization (3) is the same as the overall size of the further contact face (70), with a tolerance of at most a factor of 1.2, wherein the electrical contact metallization (3) and the further electrical contact metallization (7) may be located at opposite main sides of the semiconductor chip (2) and the semiconductor chip (2) is configured to be electrically contacted with a contact force of at least 0.3 kN/cm and of at most 2 kN/cm. The package (4) may comprise an electrically insulating jacket (41) and an electrical metal contact plate (42), wherein the semiconductor chip (2) and the electrical contact disc (5) as well as the metal plate (42) are arranged in the jacket (41) and are aligned in parallel with each other, wherein, seen in top view onto the contact face (45), sizes of the semiconductor chip (2) and the electrical contact disc (5) differ from each other by at most a factor of 1.3, and wherein the electrical contact disc (5) is located between the semiconductor chip (2) and the contact plate (42). The semiconductor chip (2), the electrical contact disc (5) and the optional contact plate (42) can be of circular shape seen in top view. The electronic device (1) may be a press pack power semiconductor device. The pressure at a given contact force is increased in the electronic device (1) by reducing the overall contact area, that is, a contact face (45) between the electrical contact metallization (3) of the semiconductor chip (2) and the electrical contact disc (5) of the package (4), to form a reliable and stable dry interface electric contact and avoid 'too low pressure1 effects, for example: for an anode side metallization of an IGCT or of an GTO, as the clamping force is typically limited for by the mechanical stability of the cathode side metallization which is in total significantly lower in contact area and more fragile due to the segmentation of a high metal stack; for a metallization of a free-floating side of a bonded diode used at low clamping forces, for example, when clamped with an IGCT - for a free-floating anode side, the probability of electromigration may be higher; or for an anode and cathode side metallization of a free-floating diode or of a free-floating plus diode clamped at relatively low pressures.

公开(公告)号：WO2022029722A1

公开(公告)日：2022-02-10

申请号：PCT/IB2021/057284

申请日：2021-08-06

申请人： MULTEK TECHNOLOGIES LIMITED

发明人： BERKEL, Jan ,  ROBINSON, Todd

IPC分类号： H05K1/02 ,  H05K1/11 ,  H01L23/498 ,  H01L23/00 ,  H05K3/46 ,  H01L21/4857 ,  H01L21/50 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/488 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L25/0657 ,  H05K1/0203 ,  H05K13/0465

摘要： Embodiments for a circuit board comprising a plurality of electrically conductive layers and a plurality of electrically non-conductive layers in a laminated stack are provided. The laminated stack defines a front face and a back face. A thermal conductive heat body extends from a die bond pad on the front face to an electrically conductive layer on the back face. The die bond pad is configured for a bare die to be mounted thereon. A bonding agent disposed around the thermal conductive heat body adhering the thermal conductive heat body to walls of an opening of the laminated stack and at least one of the plurality of electrically non- conductive layers are a monolithic structure. A plurality of wire bond pads on the front face adjacent to the die bond pad have a surface finish material thereon. The surface finish material is configured for wire bonding thereto.

公开(公告)号：WO2021243686A1

公开(公告)日：2021-12-09

申请号：PCT/CN2020/094582

申请日：2020-06-05

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： WANG, Di ,  ZHOU, Wenxi ,  XIA, Zhiliang ,  YANG, Yonggang ,  ZHANG, Kun ,  ZHANG, Hao ,  AI, Yiming

IPC分类号： H01L27/11551 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

摘要： Aspects of the disclosure provide a semiconductor device and a method for fabricating the same. The method for fabricating the semiconductor device can include forming a stack of alternating first insulating layers and first sacrificial layers over a semiconductor substrate, and forming a staircase in the stack having a plurality of steps, with at least a first step of the staircase including a first sacrificial layer of the first sacrificial layers over a first insulating layer of the first insulating layers. Further, the method can include forming a recess in the first sacrificial layer, forming a second sacrificial layer in the recess, and replacing a portion of the first sacrificial layer and the second sacrificial layer with a conductive material that forms a contact pad.

公开(公告)号：WO2021150346A1

公开(公告)日：2021-07-29

申请号：PCT/US2020/066913

申请日：2020-12-23

申请人： MICRON TECHNOLOGY, INC.

发明人： CHUN, Hyunsuk

IPC分类号： H01L21/822 ,  H01L25/065 ,  H01L27/06 ,  H01L23/48 ,  H01L21/76831 ,  H01L21/8221 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/03849 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0694

摘要： Semiconductor devices may include a die (102) including a semiconductor material. The die may include a first active surface (108) including first integrated circuitry (114) on a first side of the die and a second active surface (110) including second integrated circuitry (122) on a second, opposite side of the die. In some embodiments, the die may include two die portions: a first die portion including the first active surface and a second die portion including the second active surface. The first die portion and the second die portion may be joined together with the first active surface facing away from the second active surface.

公开(公告)号：WO2021145916A1

公开(公告)日：2021-07-22

申请号：PCT/US2020/035612

申请日：2020-06-01

申请人： SANDISK TECHNOLOGIES LLC

发明人： WU, Chen ,  RABKIN, Peter ,  HIGASHITANI, Masaaki

IPC分类号： H05K3/04 ,  H01L29/40 ,  H05K3/10 ,  H01L23/532 ,  H01L21/768 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/80001 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/89 ,  H01L25/18 ,  H01L25/50 ,  H01L27/11526 ,  H01L27/11556 ,  H01L2924/1431 ,  H01L2924/14511

摘要： A semiconductor die includes a first pad-level dielectric layer embedding first bonding pads and located over a first substrate. Each of the first bonding pads is located within a respective pad cavity in the first pad-level dielectric layer. Each of the first bonding pads includes a first metallic liner containing a first metallic liner material and contacting a sidewall of the respective pad cavity, a first metallic fill material portion embedded in the first metallic liner, and a metallic electromigration barrier layer contacting the first metallic fill material portion and adjoined to the first metallic liner.