公开(公告)号：WO2021133428A1

公开(公告)日：2021-07-01

申请号：PCT/US2020/026182

申请日：2020-04-01

申请人： SANDISK TECHNOLOGIES LLC

发明人： OKINA, Teruo

IPC分类号： H01L25/065 ,  H01L23/495 ,  H01L23/00 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76865 ,  H01L2224/05147 ,  H01L2224/08147 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/06 ,  H01L24/09

摘要： A semiconductor die includes at least one first semiconductor device located on a first substrate, a first pad-level dielectric layer which is a diffusion barrier overlying the at least one first semiconductor device, and first bonding structures including a respective first metallic bonding pad embedded in the first pad-level dielectric layer. Each of the first bonding structures includes a metallic fill material portion having a horizontal distal surface that is located within a horizontal plane including a horizontal distal surface of the first pad-level dielectric layer, and a metallic liner laterally surrounding the metallic fill material portion and vertically spaced from the horizontal plane by a vertical recess distance.

公开(公告)号：WO2023278605A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/035559

申请日：2022-06-29

申请人： INVENSAS BONDING TECHNOLOGIES, INC.

发明人： FOUNTAIN, Gaius, Gillman, Jr.

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/05546 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06138 ,  H01L2224/08147 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06565 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L2924/01029 ,  H01L2924/04642 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/059

摘要： A bonded structure is disclosed. The bonded structure can include a first element that includes a first bonding layer, the first bonding layer that has a first contact pad and a routing trace. The routing trace is formed at the same level as the first contact pad. The bonded structure can include a second element that includes a second bonding layer that has a second contact pad. The first element and the second element are directly bonded such that the first contact pad and the second contact pad are directly bonded without an intervening adhesive

公开(公告)号：WO2021133741A1

公开(公告)日：2021-07-01

申请号：PCT/US2020/066467

申请日：2020-12-21

申请人： INVENSAS BONDING TECHNOLOGIES, INC.

发明人： KATKAR, Rajesh ,  HABA, Belgacem

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L24/06 ,  H01L24/26 ,  H01L24/93 ,  H01L25/0657

摘要： An element that is configured to bond to another element is disclosed. A first element that can include a first plurality of contact pads on a first surface. The first plurality of contact pads includes a first contact pad and a second contact pad that are spaced apart from one another. The first and second contact pads are electrically connected to one another for redundancy. The first element can be prepared for direct bonding. The first element can be bonded to a second element to form a bonded structure. The second element has a second plurality of contact pads on a second surface. At least one of the second plurality of contact pads is bonded and electrically connected to at least one of the first plurality of contact pads.

公开(公告)号：WO2021076872A2

公开(公告)日：2021-04-22

申请号：PCT/US2020/055953

申请日：2020-10-16

申请人： QUALCOMM INCORPORATED

发明人： SUN, Yangyang ,  HOLMES, John ,  ZHANG, Xuefeng ,  HE, Dongming

IPC分类号： H01L23/485 ,  H01L21/60 ,  G06T7/00 ,  G06T7/0006 ,  H01L2224/037 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/1601 ,  H01L2224/16014 ,  H01L2224/16112 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2924/15747

摘要： Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.

公开(公告)号：WO2022271250A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/022615

申请日：2022-03-30

申请人： INTEL CORPORATION

发明人： ALEKSOV, Aleksandar ,  EID, Feras ,  SWAN, Johanna M. ,  ELSHERBINI, Adel A. ,  LIFF, Shawna M.

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L2224/05014 ,  H01L2224/06051 ,  H01L2224/06132 ,  H01L2224/2512 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/25 ,  H01L25/0652

摘要： Embodiments disclosed herein include semiconductor dies with hybrid bonding layers and multi-die modules that are coupled together by hybrid bonding layers. In an embodiment, a semiconductor die comprises a die substrate, a pad layer over the die substrate, where the pad layer comprises first pads with a first dimension and a first pitch and second pads with a second dimension and a second pitch. In an embodiment, the semiconductor die further comprises a hybrid bonding layer over the pad layer. In an embodiment, the hybrid bonding layer comprises a dielectric layer, and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads comprise a third dimension and a third pitch.

公开(公告)号：WO2022187776A2

公开(公告)日：2022-09-09

申请号：PCT/US2022/070496

申请日：2022-02-03

申请人： QUALCOMM INCORPORATED

发明人： ZHOU, Rong ,  ADERHOLDT, William M.

IPC分类号： H01L23/498 ,  H01L21/60 ,  H01L25/065 ,  H01L23/538 ,  H01L2224/0401 ,  H01L2224/06152 ,  H01L2224/06156 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/14152 ,  H01L2224/14156 ,  H01L2224/16157 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/214 ,  H01L2224/24137 ,  H01L2224/96 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/20 ,  H01L25/0655 ,  H01L2924/15192 ,  H01L2924/18162 ,  H01L2924/37001

摘要： Aii integrated circuit (IC) package including ICs (204) with multi- row columnar die interconnects has increased die-to-die (D2D) interconnect density in a conductive layer. Positioning the die interconnects in die interconnect column clusters (202(1), 202(2)), that each include a plurality of die interconnect rows (213,214) and two columns (200A,200B), reduces the linear dimension occupied by the die interconnects and leaves room for more D2D interconnects (206). A die interconnect column cluster pitch (Pcc2) is a distance between columns of adjacent die interconnect column clusters and this distance is greater than a die interconnect pitch (PDir2) between columns within the column clusters. Die interconnects may be disposed in the space between the multi-row column clusters and additional die interconnects can be disposed at the D2D interconnect pitch between the die interconnect column clusters. IC packages with ICs including the multi-row columnar die interconnects have a greater number of D2D interconnects for better IC integration.

公开(公告)号：WO2022096226A2

公开(公告)日：2022-05-12

申请号：PCT/EP2021/077984

申请日：2021-10-11

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： KNEISSL, Philipp ,  PFEFFERLEIN, Stefan ,  KÜRTEN, Bernd ,  WERNER, Ronny

IPC分类号： H01L23/373 ,  H01L23/488 ,  H01L21/60 ,  H01L23/498 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/29007 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/30051 ,  H01L2224/30155 ,  H01L2224/30177 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32227 ,  H01L2224/32237 ,  H01L2224/33051 ,  H01L2224/33155 ,  H01L2224/33177 ,  H01L2224/73201 ,  H01L2224/73265 ,  H01L2224/80903 ,  H01L2224/83101 ,  H01L2224/8321 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/9211 ,  H01L2224/92247 ,  H01L23/13 ,  H01L23/3735 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1431

摘要： Die Erfindung betrifft ein Halbleitermodul (2) mit zumindest einem Halbleiterelement (4) (beispielsweise einem Leistungshalbleiterelement für den Einsatz in einem Stromrichter), wobei das Halbleiterelement (4) ein Kontaktierungselement (18) aufweist, wobei das Kontaktierungselement (18) des Halbleiterelements (4) über eine Verbindungsschicht (20) stoffschlüssig mit einer metallischen Oberfläche (14) (die beispielsweise Teil eines Substrats (6) ist, das eine dielektrische Materiallage (8) sowie zumindest eine Metallisierung (10) mit der metallischen Oberfläche (14) umfasst) verbunden ist. Die stoffschlüssige Verbindung wird beispielsweise durch Löten oder Sintern hergestellt. Um das Halbleitermodul (2), im Vergleich zum Stand der Technik, einfacher und zuverlässiger zu fertigen, wird vorgeschlagen, dass die metallische Oberfläche (14) eine Kavität (22) aufweist, in welcher die Verbindungsschicht (20) angeordnet ist, wobei das Kontaktierungselement (18) die Kavität (22) zumindest teilweise überlappt. Damit wird Verkippen des Halbleiterelements (4) während der Herstellung der stoffschlüssigen Verbindung verhindert und insbesondere eine Weiterverarbeitung durch Bonden, beispielsweise Drahtbonden, einfacher und zuverlässiger erfolgen kann. Die Kavität (22) weist zumindest eine Aussparung (32) auf, über welche die Kavität (22) während der Herstellung der stoffschlüssigen Verbindung, beispielsweise während eines Lötvorgangs, entlüftet wird bzw. welche einen Gasaustausch mit der umgebenden Atmosphäre ermöglicht. Exemplarisch können Aussparungen (32) im Bereich der Ecken einer rechteckigen Grundfläche (22a) der Kavität (22) angeordnet sein. Alternativ kann eine Seitenwand (22b) der Kavität (22) teilweise über das Kontaktierungselement (18) hinausstehen, wodurch an den Kanten des Kontaktierungselements (18) jeweils Aussparungen (32) ausgebildet werden, welche den Gasaustausch mit der umgebenden Atmosphäre, beispielsweise während eines Lötvorgangs, ermöglichen. Das Kontaktierungselement (18) kann die Kavität (22) zumindest an zwei gegenüberliegenden Seiten (24, 26) und/oder vollständig überlappen. Das Kontaktierungselement (18) kann unmittelbar auf der metallischen Oberfläche (14) aufliegen oder alternativ kann sich die Verbindungsschicht (20) vollständig über das Kontaktierungselement (18) erstrecken. Eine Seitenwand (22b) der Kavität (22) kann eine zumindest teilweise umlaufende Fase (28) aufweisen, d.h. eine zumindest teilweise Abschrägung der Seitenwand (22b) der Kavität (22), die ermöglicht, dass beispielsweise ein Lot leichter der Seitenwand (22b) der Kavität (22) hochsteigt und die das Benetzen der Seitenwand (22b) mit der Verbindungsschicht (20) erleichtert. Die Kavität (22) kann ein Auflageelement (36) umfassen, das beispielsweise inselartig und im Wesentlichen mittig in der Kavität (22) angeordnet ist, wobei durch eine direkte Kontaktierung des Kontaktierungselements (18) mit dem, insbesondere aus Kupfer hergestellten, Auflageelement (36) eine verbesserte thermische Anbindung, insbesondere in einem Hauptwärmepfad, erreicht wird.

公开(公告)号：WO2022271241A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/021880

申请日：2022-03-25

申请人： INTEL CORPORATION

发明人： WAIDHAS, Bernd ,  HANNA, Carlton ,  MOREIN, Stephen ,  KESER, Lizbeth ,  SEIDEMANN, Georg

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L23/36 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/24137 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19106 ,  H05K1/181

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

公开(公告)号：WO2022043033A1

公开(公告)日：2022-03-03

申请号：PCT/EP2021/072081

申请日：2021-08-06

申请人： HITACHI ENERGY SWITZERLAND AG [CH]/[CH]

发明人： STIASNY, Thomas ,  WIKSTROEM, Tobias

IPC分类号： H01L21/603 ,  H01L23/051 ,  H01L25/10 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/04 ,  H01L2224/04042 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/48091 ,  H01L2224/73201 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/72 ,  H01L24/73 ,  H01L25/117

摘要： An electronic device (1) comprises a semiconductor chip (2) having an electrical contact metallization (3), and a package (4) having an electrical contact disc (5). The electrical contact metallization (3) and the electrical contact disc (5) are in direct contact on a contact face (45) so that the semiconductor chip (2) is electrically connected with the package (4). At the contact face (45), at least one of the electrical contact metallization (3) and the electrical contact disc (5) comprises a geometric structuring (6) (a surface pattern) fashioned as at least one recessed area. A mean roughness of a top face (50) of the electrical contact disc (5) facing the electrical contact metallization (3) may be between 0.2 pm and 1 pm, wherein, because of the mean roughness, the top face (50) is configured to penetrate an oxide layer (31) of the electrical contact metallization (3) at the contact face (45) (e.g., native oxide on an aluminum metallization (3) ). The electrical contact metallization (3) may be of multilayer fashion and comprise at least one interrupted sub-layer (33) and at least one continuous sub-layer (34), the continuous sub-layer (34) being located at the contact face (45), wherein the at least one interrupted sub-layer (33) and the at least one continuous sub-layer (34) may be of the same material or of different materials, but have different thicknesses. All of the electrical contact metallization (3) and/or of the electrical contact disc (5) may be configured to be on the same electric potential. The geometric structuring (6) may consist of or comprise at least one of the following shapes: circle, spiral, rectangle, triangle, hexagon, honeycomb and may comprise interruptions. The semiconductor chip (2) may comprise a further electrical contact metallization (7) having an even and smooth further contact face (70), wherein, seen in top view, an overall size of the further contact face (70) is smaller than that of the electrical contact metallization (3) by at least a factor of 1.5 and by at most a factor of 5, and wherein, because of the geometric structuring (6), at the contact face (45) an effective size of the electrical contact metallization (3) is the same as the overall size of the further contact face (70), with a tolerance of at most a factor of 1.2, wherein the electrical contact metallization (3) and the further electrical contact metallization (7) may be located at opposite main sides of the semiconductor chip (2) and the semiconductor chip (2) is configured to be electrically contacted with a contact force of at least 0.3 kN/cm and of at most 2 kN/cm. The package (4) may comprise an electrically insulating jacket (41) and an electrical metal contact plate (42), wherein the semiconductor chip (2) and the electrical contact disc (5) as well as the metal plate (42) are arranged in the jacket (41) and are aligned in parallel with each other, wherein, seen in top view onto the contact face (45), sizes of the semiconductor chip (2) and the electrical contact disc (5) differ from each other by at most a factor of 1.3, and wherein the electrical contact disc (5) is located between the semiconductor chip (2) and the contact plate (42). The semiconductor chip (2), the electrical contact disc (5) and the optional contact plate (42) can be of circular shape seen in top view. The electronic device (1) may be a press pack power semiconductor device. The pressure at a given contact force is increased in the electronic device (1) by reducing the overall contact area, that is, a contact face (45) between the electrical contact metallization (3) of the semiconductor chip (2) and the electrical contact disc (5) of the package (4), to form a reliable and stable dry interface electric contact and avoid 'too low pressure1 effects, for example: for an anode side metallization of an IGCT or of an GTO, as the clamping force is typically limited for by the mechanical stability of the cathode side metallization which is in total significantly lower in contact area and more fragile due to the segmentation of a high metal stack; for a metallization of a free-floating side of a bonded diode used at low clamping forces, for example, when clamped with an IGCT - for a free-floating anode side, the probability of electromigration may be higher; or for an anode and cathode side metallization of a free-floating diode or of a free-floating plus diode clamped at relatively low pressures.

公开(公告)号：WO2021150346A1

公开(公告)日：2021-07-29

申请号：PCT/US2020/066913

申请日：2020-12-23

申请人： MICRON TECHNOLOGY, INC.

发明人： CHUN, Hyunsuk

IPC分类号： H01L21/822 ,  H01L25/065 ,  H01L27/06 ,  H01L23/48 ,  H01L21/76831 ,  H01L21/8221 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/03849 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0694

摘要： Semiconductor devices may include a die (102) including a semiconductor material. The die may include a first active surface (108) including first integrated circuitry (114) on a first side of the die and a second active surface (110) including second integrated circuitry (122) on a second, opposite side of the die. In some embodiments, the die may include two die portions: a first die portion including the first active surface and a second die portion including the second active surface. The first die portion and the second die portion may be joined together with the first active surface facing away from the second active surface.