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    MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THEREOF
    1.
    发明申请
    MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THEREOF 审中-公开

    公开(公告)号：WO2023028821A1

    公开(公告)日：2023-03-09

    申请号：PCT/CN2021/115594

    申请日：2021-08-31

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： ZHU, Hongbin ,  LIU, Wei ,  WANG, Yanhong

    IPC: H01L27/108 ,  H01L27/11526 ,  H01L27/11529

    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with all sides of the semiconductor body. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

    MEMORY DEVICE WITH LATERALLY FORMED MEMORY CELLS
    2.
    发明申请
    MEMORY DEVICE WITH LATERALLY FORMED MEMORY CELLS 审中-公开

    公开(公告)号：WO2022251784A1

    公开(公告)日：2022-12-01

    申请号：PCT/US2022/072318

    申请日：2022-05-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： GRAETTINGER, Thomas M. ,  FRATIN, Lorenzo ,  FLYNN, Patrick, M. ,  VARESI, Enrico ,  FANTINI, Paolo

    IPC: H01L27/11568 ,  H01L27/11521 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11526

    Abstract: Methods, systems, and devices for a memory device with laterally formed memory cells are described. A material stack that includes a conductive layer between multiple dielectric layers may be formed, where the conductive layer and dielectric layers may form a channel in a sidewall of the material stack. The channel may be filled with one or more materials, where a first side of an outermost material of the one or more materials may be exposed. An opening may be formed in the material stack that exposes a second side of at least one material of the one or more materials. The opening may be used to replace a portion of the at least one material with a chalcogenide material where the electrode materials may be formed before replacing the portion of the at least one material with the chalcogenide material.

    INTEGRATED ASSEMBLIES AND METHODS OF FORMING INTEGRATED ASSEMBLIES
    3.
    发明申请
    INTEGRATED ASSEMBLIES AND METHODS OF FORMING INTEGRATED ASSEMBLIES 审中-公开

    公开(公告)号：WO2022216369A1

    公开(公告)日：2022-10-13

    申请号：PCT/US2022/016747

    申请日：2022-02-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： GREENLEE, Jordan, D. ,  SCARBROUGH, Alyssa, N. ,  HOPKINS, John, D.

    IPC: H01L27/11521 ,  H01L27/11568 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11526 ,  H01L27/11573

    Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block- region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped- semiconductor- material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.

    半导体存储设备及其制造方法及包括存储设备的电子设备
    5.
    发明申请
    半导体存储设备及其制造方法及包括存储设备的电子设备 审中-公开

    公开(公告)号：WO2020042253A1

    公开(公告)日：2020-03-05

    申请号：PCT/CN2018/107021

    申请日：2018-09-21

    Applicant: 中国科学院微电子研究所

    Inventor： 朱慧珑

    IPC: H01L27/11526 ,  H01L27/11573

    Abstract: 公开了一种半导体存储设备及其制造方法及包括该存储设备的电子设备。根据实施例，半导体存储设备可以包括：衬底；在衬底上按行和列排列的存储单元的阵列，各存储单元包括具有上、下源/漏区和沟道区的竖直柱状有源区以及绕沟道区外周形成的栅堆叠；在衬底上形成的分别位于相应存储单元列下方且与相应列中各存储单元下端的源/漏区电连接的多条位线；以及在衬底上形成的分别沿行的方向延伸且与相应存储单元行中各存储单元的栅堆叠电连接的多条字线，各条字线分别包括沿相应存储单元行中的存储单元的外周延伸的第一部分以及在各第一部分之间延伸的第二部分，其中，字线的第一部分与相应存储单元的至少上端源/漏区的至少部分侧壁实质上共形地延伸。

    INTEGRATED CIRCUITRY COMPRISING A MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS AND METHODS INCLUDING A METHOD USED IN FORMING A MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS
    7.
    发明申请
    INTEGRATED CIRCUITRY COMPRISING A MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS AND METHODS INCLUDING A METHOD USED IN FORMING A MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS 审中-公开

    公开(公告)号：WO2022265720A1

    公开(公告)日：2022-12-22

    申请号：PCT/US2022/024882

    申请日：2022-04-14

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： SCARBROUGH, Alyssa N. ,  GREENLEE, Jordan D. ,  HOPKINS, John D.

    IPC: H01L27/11568 ,  H01L27/11521 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11526

    Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically alternating first tiers and second insulating tiers that are of different composition relative one another. The lower portion comprises an upper polysilicon-comprising layer, a lower polysilicon- comprising layer, an intervening-material layer vertically between the upper and lower polysilicon-comprising layers. An upper intermediate layer is vertically between the upper polysilicon-comprising layer and the intervening-material layer. A lower intermediate layer is vertically between the lower polysilicon-comprising layer and the intervening-material layer. The lower intermediate layer and the upper intermediate layer comprise at least one of (a), (b), and (c), where (a): a hafnium oxide; (b): a bilayer comprising silicon nitride and comprising silicon dioxide positioned vertically relative one another, the silicon nitride in the bilayer being closer to the intervening-material layer than is the silicon dioxide in the bilayer; and (c): SiOxNy, where each of “x” and “y” is from 1 atomic percent to 90 atomic percent of the total of the Si, the O, and the N in the SiOxNy. Methods are disclosed.

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