公开(公告)号：WO1988005227A1

公开(公告)日：1988-07-14

申请号：PCT/US1987003316

申请日：1987-12-17

Applicant: GRUMMAN AEROSPACE CORPORATION

Inventor： GRUMMAN AEROSPACE CORPORATION ,  UGENTI, Michael

IPC: H03K05/24

CPC classification number: G01R19/1658 ,  G01R19/16585

Abstract: A pair of comparators (14, 22) is provided with attenuated input signals. Each comparator is provided with a different reference level (16, 30) so that two sets of complementary digital outputs (19, 21) (27, 29) may be obtained with different pusle widths. Hysteresis control (66) is provided to the comparators to compensate for noise present at the comparator inputs.

公开(公告)号：WO1996039746A1

公开(公告)日：1996-12-12

申请号：PCT/US1995011213

申请日：1995-09-06

Applicant: ANALOG DEVICES, INC. (ADI)

Inventor： ANALOG DEVICES, INC. (ADI) ,  YEE, Gaylin, M. ,  HENRY, Peter, S. ,  JENKINS, Andrew

IPC: H03K05/24

CPC classification number: H03K3/02337

Abstract: A circuit (10) and method for providing programmable hysteresis levels is disclosed. The circuit includes comparators (C1-C4) for producing output signals (V01-V04) when an input signal (V(PTAT) crosses respective set points and a hysteresis circuit (38) for establishing a hysteresis in the output signals. When a comparator's output signal is "on", the input signal is shifted by a hysteresis differential. The output signal is terminated when the shifted input signal returns to the set point. The hysteresis circuit includes a programmable hysteresis input (40) for adjusting the hysteresis differential to different preset and intermediate hysteresis levels.

Abstract translation: 公开了一种用于提供可编程磁滞电平的电路（10）和方法。 该电路包括当输入信号（V（PTAT）跨越各个设定点时产生输出信号（V01-V04）和用于在输出信号中建立迟滞的滞后电路（38）的比较器（C1-C4），当比较器 输出信号为“on”，输入信号偏移滞后差，当移位输入信号返回到设定点时，输出信号终止，滞后电路包括用于调节滞后差的可编程滞后输入（40） 不同的预设和中间滞后水平。

公开(公告)号：WO1985001845A1

公开(公告)日：1985-04-25

申请号：PCT/US1984001727

申请日：1984-10-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WONG, Thomas, S., W.

IPC: H03K05/24

CPC classification number: H03K3/286 ,  G11C7/062

Abstract: An improved sense amplifier circuit (Figs. 3, 5, 6) for sensing information in the cells (I, I) of a semiconductor memory device. The sense amplifier circuit as presented includes AC-coupled positive feedback means (40, 42 or 140, 142) to provide a reduction in sensing delay time, and thus, faster memory access time.

公开(公告)号：WO1996037046A1

公开(公告)日：1996-11-21

申请号：PCT/DE1996000858

申请日：1996-05-15

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  DRAXELMAYR, Dieter

Inventor： SIEMENS AKTIENGESELLSCHAFT

IPC: H03K05/24

CPC classification number: H03F1/083 ,  H03K5/2418

Abstract: In order to reduce the delay between the zero passage of the input voltage and the switching of the output in an analog comparator, a second transistor (T2; T20) controlled by a reference potential (VR1; VR2) is connected with its output circuit between the input and the output of a first transistor (T1) which is controlled by the output of a comparator differential stage. The saturation of said first transistor can be prevented with such a circuit.

Abstract translation: 为了减小过零点输入电压和输出的一个模拟比较器的切换之间的延迟时间，一个从参考电势（VR1，VR2）控制的第二晶体管（T2; T20）（与输入和第一晶体管的输出端之间的输出电路 T1）被连接，它是由比较差动级的输出的控制。 利用这样的电路，能够防止在第一晶体管的饱和度。

公开(公告)号：WO1995009483A1

公开(公告)日：1995-04-06

申请号：PCT/US1993009321

申请日：1993-09-30

Applicant: MACRONIX INTERNATIONAL CO., LTD. ,  NKK CORPORATION ,  LIN, Tien-Ler ,  YIU, Tom, Dang-Hsing

Inventor： MACRONIX INTERNATIONAL CO., LTD. ,  NKK CORPORATION

IPC: H03K05/24

CPC classification number: G05F3/24

Abstract: A voltage detection circuit for preventing the erasing and programming of a nonvolatile memory device during power up and power down sequences. A power source is coupled to the high voltage (Vpp) and the low voltage input (Vcc) to provide a reference voltage (Vccx) in response to the greater of the high voltage input (Vpp) or the low voltage input (Vcc). A low voltage detector (4) is coupled to the low voltage input (Vcc) and the reference voltage (Vccx) and has circuitry to provide a first not-ready signal (LVcc) when the voltage on the low input (Vcc) falls below a predetermined low voltage threshold. A high voltage detector (6) is coupled to the high voltage input (Vpp), the reference voltage (Vccx), and the output of the low voltage detector (LVcc) and has circuitry to provide a second not-ready signal (Vpph/Vdphb) when either the first non-ready signal (Vcc) is received or the voltage on the high voltage input falls below a predetermined high voltage threshold. The not-ready signals (LVcc) prevent erasing or programming operations to occur in the nonvolatile memory device.

Abstract translation: 一种用于在上电和断电序列期间防止非易失性存储器件的擦除和编程的电压检测电路。 电源耦合到高电压（Vpp）和低电压输入（Vcc），以响应于较高的高电压输入（Vpp）或低电压输入（Vcc）而提供参考电压（Vccx）。 低电压检测器（4）耦合到低电压输入（Vcc）和参考电压（Vccx），并且当低电平输入（Vcc）上的电压低于电压时，具有提供第一未就绪信号（LVcc）的电路 预定的低电压阈值。 高电压检测器（6）耦合到高电压输入（Vpp），参考电压（Vccx）和低电压检测器（LVcc）的输出，并且具有提供第二未就绪信号（Vpph / 当接收到第一非就绪信号（Vcc）或高电压输入端的电压低于预定的高电压阈值时，Vdphb）。 未就绪信号（LVcc）防止在非易失性存储器件中发生擦除或编程操作。

公开(公告)号：WO1995003651A1

公开(公告)日：1995-02-02

申请号：PCT/US1994007104

申请日：1994-06-24

Applicant: NATIONAL SEMICONDUCTOR CORPORATION

Inventor： NATIONAL SEMICONDUCTOR CORPORATION ,  RAPP, A., Karl ,  STOIAN, Lee, L.

IPC: H03K05/24

CPC classification number: H03K5/2418 ,  H03F3/45094 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45508 ,  H03F2203/45656 ,  H03F2203/45658 ,  H03K5/2481

Abstract: A voltage comparator produces a current output as a function of the differential input voltage. Three transfer functions are detailed. In the linear transfer mode the output varies linearly in the transition region and swings between zero and a well-defined current value. In a truncated response mode, the output is zero for zero differential input voltage, remains at zero for one input voltage polarity, and rises for the other polarity input linearly to a well-defined current value. In the folded response mode the output current is zero for zero differential input and rises linearly in the transition region to a well-defined current value for either polarity of differential input. While a CMOS form of construction is preferred, bipolar construction is also shown.

Abstract translation: 电压比较器产生作为差分输入电压的函数的电流输出。 详细介绍三种传递功能。 在线性传输模式下，输出在过渡区域中线性变化，并在零和定义明确的电流值之间摆动。 在截断响应模式下，零差分输入电压的输出为零，对于一个输入电压极性，输出保持为零，另一极性输入线性上升到明确定义的电流值。 在折叠响应模式下，零差分输入的输出电流为零，并且在过渡区域中线性上升到差分输入的任一极性的明确定义的电流值。 虽然优选构造CMOS形式，但是也示出了双极结构。

公开(公告)号：WO1988007290A1

公开(公告)日：1988-09-22

申请号：PCT/US1988000735

申请日：1988-03-08

Applicant: INMOS CORPORATION

Inventor： INMOS CORPORATION ,  MOBLEY, Kenneth, J.

IPC: H03K05/24

CPC classification number: H03K5/2481 ,  G11C7/062 ,  G11C2207/063 ,  H03K5/249

Abstract: An amplifier (10) for a semiconductor circuit provides two circuit paths between VCC and ground, each including the source-drain path of a corresponding primary transistor (23, 28). Two impedances (16, 18) are coupled to respective inputs (12, 14). The primary transistors are kept in saturation so that the voltage differential is developed at outputs (38, 40) located along the two circuit paths. Also, a clamp circuit has a common node (30) coupling the gate electrodes of the primary transistors together. Secondary transistors (24, 26) are included to mimic voltage changes on either input.

公开(公告)号：WO1997049184A1

公开(公告)日：1997-12-24

申请号：PCT/US1997010638

申请日：1997-06-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BREHMER, Geoffrey, E.

IPC: H03K05/24

CPC classification number: H03K5/249 ,  H03K3/35613

Abstract: A strobed comparator for a large common mode range is described, which includes a mixture of natural and enhancement transistors, and a high-swing folded-cascode architecture, to achieve an improved dynamic range suitable for audio applications.

Abstract translation: 描述了用于大共模范围的选通比较器，其包括自然和增强晶体管的混合，以及高摆幅折叠共源共栅结构，以实现适合于音频应用的改进的动态范围。

公开(公告)号：WO1992017939A1

公开(公告)日：1992-10-15

申请号：PCT/US1992002740

申请日：1992-04-03

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  VINCELETTE, Scott

IPC: H03K05/24

CPC classification number: H03K5/2481 ,  H03K3/35613 ,  H03K5/249

Abstract: An all CMOS voltage comparator circuit which incorporates a strobed latch. A strobe signal precharges the entire circuit to a known state which is independent of the input voltages and in which substantially no static current is drawn. Under static conditions after the circuit has been strobed, the source-coupled pair (52, 54) is virtually disconnected from the supply voltage(s) and draws almost no current, as well. When the circuit is strobed, a source-coupled FET pair (52, 54) amplifies the differential input signal, with positive feedback provided through a pair of cross-coupled PMOS load transistors (36, 38) as well as cross-coupled NMOS cascode transistors (46, 48). The source-coupled pair feeds a pair of output buffers (62-68) or drivers, whose FETS are sized such that a 'low' voltage level is generated on both outputs until the source-coupled pair resolves the input voltage difference (i.e., the differential input voltage exceeds the switching threshold). At that time, the outputs become complementary digital levels and are usable.

公开(公告)号：WO1991018446A1

公开(公告)日：1991-11-28

申请号：PCT/US1991003575

申请日：1991-05-21

Applicant: WAVE TECHNOLOGIES, INC.

Inventor： WAVE TECHNOLOGIES, INC. ,  STEEDEN, Terry, T. ,  LEISZ, Dennis, J. ,  BOX, Gary, W. ,  WRIGHT, Mard, D. ,  JENSEN, Mark, W. ,  HEGGE, Bradlen, J. ,  FOOTE-LENNOX, Thomas, S. ,  TURNER, John, J.

IPC: H03K05/24

CPC classification number: G01R19/0038 ,  H03K5/24

Abstract: A comparator circuit (56) constructed and arranged to change state when an unknown input waveforms voltage (sig. 1 in at 42) passes through an operator-selected trip voltage.

Abstract translation: 当未知输入波形电压（42中的信号1）通过操作者选择的跳闸电压时，构造和布置成改变状态的比较器电路（56）。