公开(公告)号：WO9428549A3

公开(公告)日：1996-06-20

申请号：PCT/US9305135

申请日：1993-05-28

Applicant: NIPPON KOKAN KK ,  MACRONIX INT CO LTD ,  LIN TIEN LER ,  YIU TOM DANG HSING ,  CHAO LIANG

Inventor： LIN TIEN-LER ,  YIU TOM DANG-HSING ,  CHAO LIANG

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/28 ,  G11C16/34 ,  G11C29/50 ,  G11C

CPC classification number: G11C16/3445 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/0491 ,  G11C16/28 ,  G11C16/3436 ,  G11C16/3459 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5004

Abstract: For non-volatile memory devices, such as flash EPROM integrated circuits, which have memory cells (10) and reference cells (23), and sense circuitry (27) responsive to addressed memory cells (10) and the reference cells (23), and in which a read potential is supplied to the gate of the selected memory cells and a reference potential is supplied to the gate of a reference memory cell during a read mode, the state of the programmable memory cells (10) is verified by (1) supplying a first verify potential to the gate of an address programmable memory cell; and (2) supplying a second verify potential to the gate of the reference cell which is different from the first verify potential. Because cell current is a very strong function of the gate voltage, applying different gate voltages to the memory (10) and reference cells (23) is equivalent to adjusting the sense ratio.

公开(公告)号：WO1995009483A1

公开(公告)日：1995-04-06

申请号：PCT/US1993009321

申请日：1993-09-30

Applicant: MACRONIX INTERNATIONAL CO., LTD. ,  NKK CORPORATION ,  LIN, Tien-Ler ,  YIU, Tom, Dang-Hsing

Inventor： MACRONIX INTERNATIONAL CO., LTD. ,  NKK CORPORATION

IPC: H03K05/24

CPC classification number: G05F3/24

Abstract: A voltage detection circuit for preventing the erasing and programming of a nonvolatile memory device during power up and power down sequences. A power source is coupled to the high voltage (Vpp) and the low voltage input (Vcc) to provide a reference voltage (Vccx) in response to the greater of the high voltage input (Vpp) or the low voltage input (Vcc). A low voltage detector (4) is coupled to the low voltage input (Vcc) and the reference voltage (Vccx) and has circuitry to provide a first not-ready signal (LVcc) when the voltage on the low input (Vcc) falls below a predetermined low voltage threshold. A high voltage detector (6) is coupled to the high voltage input (Vpp), the reference voltage (Vccx), and the output of the low voltage detector (LVcc) and has circuitry to provide a second not-ready signal (Vpph/Vdphb) when either the first non-ready signal (Vcc) is received or the voltage on the high voltage input falls below a predetermined high voltage threshold. The not-ready signals (LVcc) prevent erasing or programming operations to occur in the nonvolatile memory device.

Abstract translation: 一种用于在上电和断电序列期间防止非易失性存储器件的擦除和编程的电压检测电路。 电源耦合到高电压（Vpp）和低电压输入（Vcc），以响应于较高的高电压输入（Vpp）或低电压输入（Vcc）而提供参考电压（Vccx）。 低电压检测器（4）耦合到低电压输入（Vcc）和参考电压（Vccx），并且当低电平输入（Vcc）上的电压低于电压时，具有提供第一未就绪信号（LVcc）的电路 预定的低电压阈值。 高电压检测器（6）耦合到高电压输入（Vpp），参考电压（Vccx）和低电压检测器（LVcc）的输出，并且具有提供第二未就绪信号（Vpph / 当接收到第一非就绪信号（Vcc）或高电压输入端的电压低于预定的高电压阈值时，Vdphb）。 未就绪信号（LVcc）防止在非易失性存储器件中发生擦除或编程操作。

公开(公告)号：WO1994028551A1

公开(公告)日：1994-12-08

申请号：PCT/US1993005146

申请日：1993-05-28

Applicant: NKK CORPORATION ,  MACRONIX INTERNATIONAL CO., LTD. ,  LIN, Tien-Ler ,  WAN, Ray, L. ,  HSIAO, Ling-Wen ,  SUNG, Gilbert

Inventor： NKK CORPORATION ,  MACRONIX INTERNATIONAL CO., LTD.

IPC: G11C07/00

CPC classification number: G11C16/16

Abstract: A FLASH EPROM device comprises a memory array (10) organized into a plurality of blocks of memory cells. An energizing circuit applies energizing voltages to the blocks of memory cells to read and program addressed cells, and to erase selected blocks or the whole memory array (10). An erase verify circuit (12) separately verifies erasure of blocks in the plurality of block memory cells. Control logic controls the energizing circuit to re-erase blocks which fail erase verify. The control logic includes a plurality of block erase flags (13) which correspond to respective blocks of memory cells in the array (10). The erase verify is responsive to the block erase flags (13) to verify only those blocks having a set block erase flag. If the block passes erase verify, then the block erase flag is reset.

Abstract translation: 闪存EPROM设备包括组织成多个存储单元块的存储器阵列（10）。 激励电路向存储器单元的块施加通电电压以读取和编程寻址单元，并擦除所选择的块或整个存储器阵列（10）。 擦除验证电路（12）分别验证多个块存储单元中的块的擦除。 控制逻辑控制通电电路重新擦除擦除验证失败的块。 控制逻辑包括与阵列（10）中的存储器单元的各个块对应的多个块擦除标志（13）。 擦除验证响应于块擦除标志（13）以仅验证具有设置块擦除标志的那些块。 如果块通过擦除验证，则块擦除标志被复位。

公开(公告)号：WO2005067536A3

公开(公告)日：2006-02-02

申请号：PCT/US2005000131

申请日：2005-01-03

Applicant: INTEGRATED MEMORY TECH INC ,  JENQ CHING-SHI ,  LIN TIEN-LER

Inventor： JENQ CHING-SHI ,  LIN TIEN-LER

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C16/0483 ,  G11C16/0491 ,  G11C16/24

Abstract: An integrated circuit memory device has an array of non-floating gate non-volatile flash cells arranged in a NOR configuration. The device further has page buffers and control circuits to operate the array in either a NAND mode of operation or a NOR mode of operation. Finally, the array is partitionable by a user into two partitions such that one partition operates only in the NAND mode while the other partition operates only in a NOR mode.

Abstract translation: 集成电路存储器件具有以NOR配置布置的非浮动栅极非易失性闪存单元的阵列。 器件还具有页缓冲器和控制电路，以在NAND操作模式或NOR操作模式下操作阵列。 最后，阵列可由用户分割成两个分区，使得一个分区仅在NAND模式下操作，而另一个分区仅在NOR模式下操作。

公开(公告)号：WO1996008821A1

公开(公告)日：1996-03-21

申请号：PCT/US1994010331

申请日：1994-09-13

Applicant: MACRONIX INTERNATIONAL CO., LTD. ,  NKK CORPORATION ,  YIU, Tom, Dang-Hsing ,  SHONE, Fuchia ,  LIN, Tien-Ler ,  WAN, Ray, L.

Inventor： MACRONIX INTERNATIONAL CO., LTD. ,  NKK CORPORATION

IPC: G11C07/00

CPC classification number: G11C8/12 ,  G08G1/017 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/16 ,  H01L27/115 ,  H01L27/11521

Abstract: Contactless flash EPROM cell and array designs, and methods for fabricating the same result in a dense, segmentable flash EPROM chip. The flash EPROM cell (75-1, 75-n, 76-1, 76-n) is based on a drain-source-drain configuration, in which the single source diffusion is shared by two columns of transistors. The module includes a memory array having at least M rows and two N columns of flash EPROM cells. M word lines (WL1-WLN), each coupled to the flash EPROM cells in one of the M rows of the flash EPROM cells, and N global bit lines (83, 84) are included. Data in and out circuitry is coupled to the N global bit lines which provide for reading and writing data in the memory array.

Abstract translation: 非接触式闪存EPROM单元和阵列设计及其制造方法产生密集，可分割的闪存EPROM芯片。 闪存EPROM单元（75-1,75-n，76-1,76-n）基于漏 - 源 - 漏配置，其中单个源扩散由两列晶体管共享。 该模块包括具有至少M行和两列N列闪速EPROM单元的存储器阵列。 M字线（WL1-WLN）各自耦合到闪存EPROM单元的M行之一中的闪存EPROM单元和N个全局位线（83,84）。 数据输入和输出电路耦合到提供在存储器阵列中的数据读取和写入的N个全局位线。

公开(公告)号：WO1996038845A1

公开(公告)日：1996-12-05

申请号：PCT/US1995006990

申请日：1995-05-31

Applicant: MACRONIX INTERNATIONAL CO., LTD. ,  LIOU, Kong-Mou ,  YIU, Tom, Dang-Hsing ,  WAN, Ray-Lin ,  CHENG, Yao-Wu ,  HUNG, Chun-Hsiung ,  LIN, Tien-Ler ,  HU, Ting-Chung

Inventor： MACRONIX INTERNATIONAL CO., LTD.

IPC: G11C07/00

CPC classification number: G11C29/76 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/08

Abstract: A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated memory array having a plurality of sectors (10) selected by an address decoder (11, 13) in response to an N bit field in an address (17). If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder (12) to prevent access to the defective sectors while maintaining sequential addressing remaining in the array. The step of partitioning includes configuring the sector decoder (12) to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the address bits in common with the defective sector when m is between 1 and N-1.

Abstract translation: 用于提高高密度存储器件（例如闪速EEPROM）的制造成品率的灵活技术涉及重新配置具有响应于N位的地址解码器（11,13）选择的多个扇区（10）的集成存储器阵列 字段中的一个地址（17）。 如果在阵列中检测到有缺陷的扇区，则通过配置扇区解码器（12）来分区以禁用缺陷扇区，以阻止对缺陷扇区的访问，同时保持阵列中的顺序寻址。 分割步骤包括配置扇区解码器（12），以便当m在1之间时，具有与缺陷扇区相同的地址位的Nm的阵列的另一半中的阵列的一半中的缺陷扇区 和N-1。

公开(公告)号：WO1996008840A1

公开(公告)日：1996-03-21

申请号：PCT/US1994010276

申请日：1994-09-13

Applicant: MACRONIX INTERNATIONAL CO., LTD. ,  NKK CORPORATION ,  SHONE, Fuchia ,  YIU, Tom, Dang-Hsing ,  LIN, Tien, Ler

Inventor： MACRONIX INTERNATIONAL CO., LTD. ,  NKK CORPORATION

IPC: H01L21/265

CPC classification number: H01L27/11519 ,  G11C16/10 ,  G11C29/82 ,  H01L27/115 ,  H01L27/11521

Abstract: Contactless flash EPROM cell/array designs, and methods for fabricating the same result in dense, segmentable flash EPROM chips. An extended floating gate structure allows for higher capacitive coupling ratios in flash EPROMs with very small design rules. The floating gates are extended in a drain-source-drain architecture so that each pair of cells has a floating gate which is extended in opposite directions from one another, allowing use of cell space normally consumed by isolation regions to extend the floating gates without increasing cell layout. Also, an easily scalable design is based on establishing conductive spacers (240-241) on the sides of floating gate deposition layers (204, 242). A floating gate deposition (204, 242) is first laid down and used for establishing self-aligned source and drain regions (213-215). After forming the source and drain (213-215), conductive spacers (240-241) are deposited in a symmetrical fashion on the sides of the first floating gate structure (204, 242).

Abstract translation: 非接触式闪存EPROM单元/阵列设计及其制造方法产生致密的，可分割的闪存EPROM芯片。 扩展浮栅结构允许具有非常小的设计规则的闪存EPROM中的更高的电容耦合比。 浮置栅极在漏 - 源 - 漏极结构中延伸，使得每对单元具有彼此相反方向延伸的浮置栅极，允许使用通常由隔离区消耗的单元空间来扩展浮置栅极而不增加 单元布局。 此外，易于扩展的设计是基于在浮栅沉积层（204,242）的侧面上建立导电间隔物（240-241）。 首先放置浮置栅极沉积（204,242）并用于建立自对准的源极和漏极区域（213-215）。 在形成源极和漏极（213-215）之后，导电间隔物（240-241）以对称的方式沉积在第一浮栅结构（204,242）的侧面上。

公开(公告)号：WO2005067536A2

公开(公告)日：2005-07-28

申请号：PCT/US2005/000131

申请日：2005-01-03

Applicant: INTEGRATED MEMORY TECHNOLOGIES, INC. ,  JENQ, Ching-Shi ,  LIN, Tien-Ler

Inventor： JENQ, Ching-Shi ,  LIN, Tien-Ler

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C16/0483 ,  G11C16/0491 ,  G11C16/24

Abstract: An integrated circuit memory device has an array of non-floating gate non-volatile flash cells arranged in a NOR configuration. The device further has page buffers and control circuits to operate the array in either a NAND mode of operation or a NOR mode of operation. Finally, the array is partitionable by a user into two partitions such that one partition operates only in the NAND mode while the other partition operates only in a NOR mode.

Abstract translation: 集成电路存储器件具有以NOR配置布置的非浮动栅极非易失性闪存单元的阵列。 器件还具有页缓冲器和控制电路，以在NAND操作模式或NOR操作模式下操作阵列。 最后，阵列可由用户分割成两个分区，使得一个分区仅在NAND模式下操作，而另一个分区仅在NOR模式下操作。

公开(公告)号：WO1996021229A1

公开(公告)日：1996-07-11

申请号：PCT/US1995000079

申请日：1995-01-05

Applicant: MACRONIX INTERNATIONAL CO., LTD. ,  LIN, Tien-Ler

Inventor： MACRONIX INTERNATIONAL CO., LTD.

IPC: G11C29/00

CPC classification number: G11C29/44 ,  G06F11/076

Abstract: A non-volatile memory device (10) includes read, erase, program and verify control logic. A status register (38) is coupled with the control logic and stores statistics determined during verify operations. For instance, the statistics may indicate a number of memory cells which fail erase or program verify or may indicate whether a threshold number of sequential bytes fail program verify for a program or erase operation involving a page or sector of data. Defective addresses can also be stored. With the status register (38) the number of program and erase retries can be significantly reduced, allowing application of the device to real time storage system. The user can rely on the status register (38) to indicate how many errors have been detected in the array and if more than a threshold number of errors is detected, then the data can be discarded.

Abstract translation: 非易失性存储器件（10）包括读取，擦除，编程和验证控制逻辑。 状态寄存器（38）与控制逻辑耦合并存储在验证操作期间确定的统计信息。 例如，统计可以指示多个存储器单元，其不能擦除或程序验证，或者可以指示阈值数量的顺序字节是否对于涉及页面或扇区数据的程序或擦除操作的程序验证失败。 还可以存储不良地址。 使用状态寄存器（38）可以大大减少编程和擦除重试次数，从而允许将设备应用于实时存储系统。 用户可以依靠状态寄存器（38）来指示在阵列中检测到多少个错误，并且如果检测到多于一个阈值数量的错误，则可以丢弃该数据。

公开(公告)号：WO1995009424A1

公开(公告)日：1995-04-06

申请号：PCT/US1993009317

申请日：1993-09-30

Applicant: MACRONIX INTERNATIONAL CO., LTD. ,  NKK CORPORATION ,  LIN, Tien-Ler ,  YIU, Tom, Dang-Hsing ,  WAN, Ray, L. ,  LIOU, Kong-Mou

Inventor： MACRONIX INTERNATIONAL CO., LTD. ,  NKK CORPORATION

IPC: G11C29/00

CPC classification number: G11C29/48 ,  G11C29/44

Abstract: An integrated circuit (1) comprises a functional module (2) such as a FLASH memory with automatic program and erase circuits, test circuitry (3) coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuitry in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port (5) is provided on the integrated circuit coupled to the non-volatile memory (4) through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array. Program and erase circuitry, coupled to the array, has a test mode to exercise the program and erase circuitry to generate status information indicating results of the test and test read mode to read out the status information. Non-volatile status write circuitry is coupled to the program and erase circuitry and the test set, and writes the status information to the test set. The program and erase circuits include retry counts with programmable thresholds for reducing the test times of the devices.

Abstract translation: 集成电路（1）包括诸如具有自动编程和擦除电路的闪速存储器的功能模块（2），与功能模块耦合的测试电路（3），其执行功能模块的测试并产生状态信息 的测试和非易失性状态写入电路与芯片上的测试电路耦合。 非易失性状态写入电路中的电路响应于功能电路的测试，以将状态信息写入非易失性存储器。 在集成电路上提供端口（5），该集成电路耦合到非易失性存储器（4），存储在非易失性存储器中的状态信息可通过该端口以测试读取模式访问到外部设备。 在FLASH EPROM实施例中，IC包括闪存EPROM存储器单元阵列和阵列中的数据可由外部设备访问的端口。 阵列中提供了一组FLASH EPROM存储单元。 耦合到阵列的编程和擦除电路具有运行程序和擦除电路的测试模式，以产生指示测试结果的状态信息和测试读取模式以读出状态信息。 非易失性状态写入电路耦合到程序和擦除电路和测试集，并将状态信息写入测试集。 程序和擦除电路包括具有可编程阈值的重试计数，以减少器件的测试时间。