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    DECK SELECTION LAYOUTS IN A MEMORY DEVICE
    1.
    发明申请
    DECK SELECTION LAYOUTS IN A MEMORY DEVICE 审中-公开

    公开(公告)号：WO2023091862A1

    公开(公告)日：2023-05-25

    申请号：PCT/US2022/079405

    申请日：2022-11-07

    申请人： MICRON TECHNOLOGY, INC.

    发明人： VIMERCATI, Daniele

    IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C8/14

    摘要： Methods, systems, and devices for deck selection layouts in a memory device are described. In some implementations, a tile of a memory array may be associated with a level above a substrate, and may include a set of memory cells, a set of digit lines, and a set of word lines. Selection transistors associated with a tile of memory cells may be operable for coupling digit lines of the tile with circuitry outside the tile, and may be activated by various configurations of one or more access lines, where the various configurations may be implemented to trade off or otherwise support design and performance characteristics such as power consumption, layout complexity, operational complexity, and other characteristics. Such techniques may be implemented for other aspects of tile operations, including memory cell shunting or equalization, tile selection using transistors of a different level, or signal development, or various combinations thereof.

    一种嵌入式半导体随机存取存储器结构及其控制方法
    5.
    发明申请
    一种嵌入式半导体随机存取存储器结构及其控制方法 审中-公开

    公开(公告)号：WO2023087804A1

    公开(公告)日：2023-05-25

    申请号：PCT/CN2022/112021

    申请日：2022-08-12

    申请人： 北京大学

    发明人： 黄芊芊 ,  王凯枫 ,  符芷源 ,  黄如

    IPC分类号： G11C11/409 ,  H01L27/24

    摘要： 一种嵌入式半导体随机存取存储器结构，包括一个用于存储信息的铪基铁电存储单元和一个连接存储单元的隧穿场效应晶体管，隧穿场效应晶体管用于对所述铪基铁电存储单元进行控制，进行写操作和读操作。多个所述存储器结构组成半导体存储器阵列，其控制方法包括写0、写1、读取和重写步骤。本发明利用隧穿场效应晶体管单向导通特性和极低漏电流特性，可以降低存储器阵列的操作电压和功耗，提升存储器集成密度，适用于半导体存储器芯片的制造，且其控制方法和电路也较为简单。

    POWER SUPPLY TRACKING CIRCUITRY FOR EMBEDDED MEMORIES
    8.
    发明申请
    POWER SUPPLY TRACKING CIRCUITRY FOR EMBEDDED MEMORIES 审中-公开

    公开(公告)号：WO2023076038A1

    公开(公告)日：2023-05-04

    申请号：PCT/US2022/046622

    申请日：2022-10-13

    申请人： SYNOPSYS, INC.

    发明人： PILO, Harold ,  KUMAR, Shishir ,  GARG, Anurag

    IPC分类号： G11C7/22 ,  G11C8/18 ,  G11C11/417 ,  G11C5/14

    摘要： Tracking circuitry for a memory device including an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted level shifted clock signal. The logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal. The tracking circuitry may be added to a clock buffer to align a data clock signal with a wordline signal and a write signal, thus improving the performance of the memory device.

    一种半导体结构及其制作方法
    10.
    发明申请
    一种半导体结构及其制作方法 审中-公开

    公开(公告)号：WO2023071141A1

    公开(公告)日：2023-05-04

    申请号：PCT/CN2022/092200

    申请日：2022-05-11

    申请人： 长鑫存储技术有限公司

    发明人： 韩清华

    IPC分类号： H01L27/108 ,  G11C16/04 ,  H01L27/115 ,  H01L23/528 ,  H01L21/8242

    摘要： 本公开实施例提供了一种半导体结构及其制作方法，将半导体结构中字线与位线交叉，且将位线设置呈锯齿形弯折线，使得交叉位置设置的垂直晶体管呈六角密堆排布，降低了无用区域的面积占比，避免了面积浪费，解决了现有技术的制造方法中形成的四方结构的交叉阵列在制作存储电容时并不具备最高面积效率的问题。