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    BISBX (012) LAYERS HAVING INCREASED OPERATING TEMPERATURES FOR SOT AND MRAM DEVICES
    2.
    发明申请
    BISBX (012) LAYERS HAVING INCREASED OPERATING TEMPERATURES FOR SOT AND MRAM DEVICES 审中-公开

    公开(公告)号：WO2023022764A1

    公开(公告)日：2023-02-23

    申请号：PCT/US2022/027960

    申请日：2022-05-06

    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

    Inventor： LE, Quang ,  YORK, Brian R. ,  HWANG, Cherngye ,  OKAMURA, Susumu ,  LIU, Xiaoyong ,  HO, Kuok San ,  TAKANO, Hisashi

    IPC: H01L43/10 ,  H01L43/12 ,  H01L43/02 ,  H01L27/22

    Abstract: The present disclosure generally relate to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a topological insulator (TI) modulation layer. The TI modulation layer comprises a plurality of bismuth or bismuth-rich composition modulation layers, a plurality of TI lamellae layers comprising BiSb having a (012) crystal orientation, and a plurality of texturing layers. The TI lamellae layers comprise dopants or clusters of atoms, the clusters of atoms comprising a carbide, a nitride, an oxide, or a composite ceramic material. The clusters of atoms are configured to have a grain boundary glass forming temperature of less than about 400°C. Doping the TI lamellae layers comprising BiSb having a (012) crystal orientation with clusters of atoms comprising a carbide, a nitride, an oxide, or a composite ceramic material enable the SOT MTJ device to operate at higher temperatures while inhibiting migration of Sb from the BiSb of the TI lamellae layers.

    磁気センサ及び磁気検知システム
    4.
    发明申请
    磁気センサ及び磁気検知システム 审中-公开

    公开(公告)号：WO2022244735A1

    公开(公告)日：2022-11-24

    申请号：PCT/JP2022/020402

    申请日：2022-05-16

    Applicant: パナソニックＩＰマネジメント株式会社

    Inventor： 尾中　和弘 ,  小原　直樹

    IPC: H01L43/02 ,  H01L43/08 ,  G01R33/09

    Abstract: 本開示は、磁気センサに印加される磁界の向きの検知精度を向上させることを目的とする。磁気センサ（１００）は、第１ハーフブリッジ回路（Ｈ１）と、第２ハーフブリッジ回路と、保持部材と、を備える。第１ハーフブリッジ回路（Ｈ１）は、第１磁気抵抗効果素子（Ｍｒ１）及び第２磁気抵抗効果素子（Ｍｒ２）を有する。第２ハーフブリッジ回路は、第３磁気抵抗効果素子及び第４磁気抵抗効果素子を有する。第１磁気抵抗効果素子（Ｍｒ１）は、Ｘ軸に沿った磁界を検知する。第２磁気抵抗効果素子（Ｍｒ２）は、Ｙ軸に沿った磁界を検知する。第３磁気抵抗効果素子は、第１軸（Ｖ軸）に沿った磁界を検知する。第４磁気抵抗効果素子は、第２軸（Ｗ軸）に沿った磁界を検知する。

    SPIN ORBIT TORQUE MRAM AND MANUFACTURE THEREOF
    6.
    发明申请
    SPIN ORBIT TORQUE MRAM AND MANUFACTURE THEREOF 审中-公开

    公开(公告)号：WO2020106378A1

    公开(公告)日：2020-05-28

    申请号：PCT/US2019/055886

    申请日：2019-10-11

    Applicant: APPLIED MATERIALS, INC.

    Inventor： AHN, Jaesoo ,  PARK, Chando ,  TSENG, Hsin-Wei ,  XUE, Lin ,  PAKALA, Mahendra

    IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

    Abstract: Disclosed herein is an improved SOT-MRAM device and method of manufacture thereof. A memory device includes a first structure that includes a magnetic tunnel junction stack and a spin-orbit torque layer. The spin-orbit torque layer is formed on the magnetic tunnel junction stack. A dielectric capping layer is formed over the spin-orbit torque layer. A metal layer is formed on top of the first structure. The metal layer surrounds each of the spin-orbit torque layer and the dielectric capping layer. The metal layer is in direct contact with a sidewall of the spin-orbit torque layer.

    메모리 소자
    7.
    发明申请
    메모리 소자 审中-公开

    公开(公告)号：WO2020105877A1

    公开(公告)日：2020-05-28

    申请号：PCT/KR2019/014086

    申请日：2019-10-24

    Applicant: 한양대학교 산학협력단

    Inventor： 박재근 ,  백종웅

    IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10

    Abstract: 본 발명은 메모리 소자를 개시한다. 본 발명의 실시예에 따른 메모리 소자는 기판 상에 형성되는 하부 전극, 시드층, 합성 교환 반자성층, 자기 터널 접합 및 상부 전극이 적층 되고, 상기 자기 터널 접합은 고정층, 터널 배리어층 및 자유층을 포함하며, 상기 자유층은 제1 자유층, 분리층(spacer layer), 결합층(coupling layer), 버퍼층(buffer layer) 및 제2 자유층이 순차적으로 적층으로 한다.

    METHODS TO FORM TOP CONTACT TO A MAGNETIC TUNNEL JUNCTION
    8.
    发明申请
    METHODS TO FORM TOP CONTACT TO A MAGNETIC TUNNEL JUNCTION 审中-公开

    公开(公告)号：WO2020068327A1

    公开(公告)日：2020-04-02

    申请号：PCT/US2019/048134

    申请日：2019-08-26

    Applicant: APPLIED MATERIALS, INC.

    Inventor： XUE, Lin ,  AHN, Jaesoo ,  TSENG, Hsin-wei ,  PAKALA, Mahendra

    IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02

    Abstract: Embodiments of the disclosure relate to methods for fabricating structures used in memory devices. More specifically, embodiments of the disclosure relate to methods for fabricating MTJ structures in memory devices. In one embodiment, the method includes forming a MTJ structure, depositing a encapsulating layer on a top and sides of the MTJ structure, depositing a dielectric material on the encapsulating layer, removing the dielectric material and the encapsulating layer disposed on the top of the MTJ structure by a chemical mechanical planarization (CMP) process to expose the top of the MTJ structure, and depositing a contact layer on the MTJ structure. The method utilizes a CMP process to expose the top of the MTJ structure instead of an etching process, which avoids damaging the MTJ structure and leads to improved electrical contact between the MTJ structure and the contact layer.

    메모리 소자
    9.
    发明申请
    메모리 소자 审中-公开

    公开(公告)号：WO2019143052A1

    公开(公告)日：2019-07-25

    申请号：PCT/KR2019/000133

    申请日：2019-01-04

    Applicant: 한양대학교 산학협력단

    Inventor： 박재근 ,  최진영 ,  전한솔 ,  이동기 ,  케이콘도 ,  백종웅

    IPC: H01L43/08 ,  H01L43/02

    CPC classification number: H01L43/02 ,  H01L43/08

    Abstract: 본 발명은 메모리 소자를 개시한다. 본 발명의 실시예에 따른 메모리 소자는 기판 상에 형성되는 하부 전극, 시드층, 하부 합성 교환 반자성층, 자기 터널 접합, 상부 합성 교환 반자성층 및 상부 전극이 적층 되고, 상기 자기 터널 접합은, 하부 고정층, 하부 터널 배리어층, 하부 자유층, 분리층, 상부 자유층, 상부 터널 배리어층 및 상부 고정층이 순차적으로 적층된 것을 특징으로 한다.

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