中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

321 records (took 0.02 seconds)

    LOW LATENCY, BROADBAND POWER-DOMAIN OFFSET-CORRECTION SIGNAL LEVEL CIRCUIT IMPLEMENTATION
    1.
    发明申请
    LOW LATENCY, BROADBAND POWER-DOMAIN OFFSET-CORRECTION SIGNAL LEVEL CIRCUIT IMPLEMENTATION 审中-公开

    公开(公告)号：WO2023014491A1

    公开(公告)日：2023-02-09

    申请号：PCT/US2022/037377

    申请日：2022-07-15

    Applicant: AYDEEKAY LLC DBA INDIE SEMICONDUCTOR

    Inventor： RADFAR, Mohammad ,  AOKI, Ichiro ,  KEE, Scott, David

    IPC: H02M3/07 ,  H03K3/3568 ,  H03K3/35 ,  H03K3/353 ,  H03K3/356

    Abstract: An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.

    TRUE SINGLE PHASE CLOCK (TSPC) BASED LATCH ARRAY
    2.
    发明申请
    TRUE SINGLE PHASE CLOCK (TSPC) BASED LATCH ARRAY 审中-公开

    公开(公告)号：WO2022164633A1

    公开(公告)日：2022-08-04

    申请号：PCT/US2022/012108

    申请日：2022-01-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： LI, Rui ,  LU, De ,  NARAYANAN, Venkat

    IPC: G11C19/28 ,  H03K3/356

    Abstract: A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOl) gate cross-coupled with a NOR gate to receive and latch the data from, the master latch, and an inverter including an input coupled to the AOT gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.

    STATIC AND INTERMITTENT DYNAMIC MULTI-BIAS CORE FOR DUAL PAD VOLTAGE LEVEL SHIFTER
    3.
    发明申请
    STATIC AND INTERMITTENT DYNAMIC MULTI-BIAS CORE FOR DUAL PAD VOLTAGE LEVEL SHIFTER 审中-公开

    公开(公告)号：WO2022081321A1

    公开(公告)日：2022-04-21

    申请号：PCT/US2021/051697

    申请日：2021-09-23

    Applicant: QUALCOMM INCORPORATED

    Inventor： PRESSWALA, Aliasgar ,  CHEN, Wilson Jianbo ,  TAN, Chiew-Guan ,  JALILIZEINALI, Reza

    IPC: H03K3/356

    Abstract: An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.

    半導体装置
    6.
    发明申请
    半導体装置 审中-公开

    公开(公告)号：WO2021059580A1

    公开(公告)日：2021-04-01

    申请号：PCT/JP2020/019307

    申请日：2020-05-14

    Applicant: ヌヴォトンテクノロジージャパン株式会社

    Inventor： 中西　和幸 ,  平田　昭夫

    IPC: H01L27/04 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H03K3/356

    Abstract: 本開示の一態様に係る半導体装置は、複数の配線層（Ｍ１～Ｍ３）と、第１配線（１１）と、第１配線（１１）と接続されず、かつ、第１配線（１１）と同じ信号レベルを伝達するために冗長に設けられた第２配線（１２）と、を備え、第１配線（１１）と第２配線（１２）とは異なる配線層に属し、第１配線（１１）と第２配線（１２）との距離は、隣り合う配線層の層間距離ｃより大きい。

    データ保持回路
    7.
    发明申请
    データ保持回路 审中-公开

    公开(公告)号：WO2020079951A1

    公开(公告)日：2020-04-23

    申请号：PCT/JP2019/032774

    申请日：2019-08-22

    Applicant: ソニーセミコンダクタソリューションズ株式会社

    Inventor： 川上　敦史

    IPC: H03K3/037 ,  H03K3/356

    Abstract: データ保持回路を小型化する。　第１および第２のＭＯＳトランジスタは、クロック信号が第１のレベルのときに状態保持回路を構成する第１および第２の反転ゲートの入力にデータ信号および反転データ信号をそれぞれ伝達する。第５および第６のＭＯＳトランジスタは、第２の反転ゲートの出力から第１の反転ゲートの入力への帰還経路および第１の反転ゲートの出力から第２の反転ゲートの入力への帰還経路にそれぞれ挿入されてクロック信号が第２の信号レベルのときに第２および第１の反転ゲートの出力をそれぞれ伝達する。第７および第８のＭＯＳトランジスタは、第１のＭＯＳトランジスタとは異なる導電型チャネルに構成されるとともに第５および第６のＭＯＳトランジスタにそれぞれ並列に接続され、反転データ信号およびデータ信号に基づいて第２の反転ゲートの出力および第１の反転ゲートの出力をそれぞれ伝達する。

    MULTI-MODE POWER TRAIN INTEGRATED CIRCUIT
    8.
    发明申请
    MULTI-MODE POWER TRAIN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：WO2019036154A1

    公开(公告)日：2019-02-21

    申请号：PCT/US2018/043024

    申请日：2018-07-20

    Applicant: WITRICITY CORPORATION

    Inventor： DER, Lawrence ,  GUPTA, Sanjay

    IPC: H03K3/356 ,  H03K19/094 ,  H03K17/10 ,  G05F3/20 ,  H03K19/003 ,  H03K19/017

    CPC classification number: H03K3/356182 ,  G05F3/205 ,  H03K3/35613 ,  H03K17/102 ,  H03K19/00315 ,  H03K19/01721 ,  H03K19/09429

    Abstract: A configurable driver integrated circuit is disclosed having a plurality of input/output terminals for interfacing exterior of the integrated circuit. The integrated circuit includes a plurality of driver circuits, with each driver circuit including a transistor having a source and a drain, and each of the source and drain thereof connected to a dedicated and respective one of the input/output terminals and further includes a gate driver for driving a gate of the transistor, with supply inputs associated with a floating voltage domain, and each driver circuit also includes a level shift circuit for shifting the level of a logic signal from a fixed voltage domain to the floating voltage domain. A switching circuitry generates switching signals in a fixed voltage domain for controlling the operation of each of the driver circuits in accordance with a predetermined configuration defined by external circuit.

    DATA RETENTION WITH DATA MIGRATION
    9.
    发明申请
    DATA RETENTION WITH DATA MIGRATION 审中-公开

    公开(公告)号：WO2018190959A1

    公开(公告)日：2018-10-18

    申请号：PCT/US2018/019714

    申请日：2018-02-26

    Applicant: QUALCOMM INCORPORATED

    Inventor： ORUGANTI, Kalyan Kumar ,  DIGARI, Kailash ,  SRIVATSA, Sandeep Nellikatte

    IPC: G06F1/32 ,  G11C14/00 ,  H03K3/356

    Abstract: An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The logic block includes multiple retention‑relevant storage devices to store first data and second data. The multiple retention-relevant storage devices include a first group of retention‑relevant storage devices to store the first data and a second group of retention-relevant storage devices to store the second data. The memory block maintains memory data in the memory block during a retention operational mode. The retention control circuitry causes the retention-relevant storage devices of the second group to be activated into multiple scan chains and also migrates the second data between the second group and the memory block using the multiple scan chains to accommodate transitions between the retention operational mode and a regular operational mode.

    LAYOUTS OF TRANSMISSION GATES AND RELATED SYSTEMS AND TECHNIQUES
    10.
    发明申请
    LAYOUTS OF TRANSMISSION GATES AND RELATED SYSTEMS AND TECHNIQUES 审中-公开
    传输门及其相关系统和技术

    公开(公告)号：WO2017118873A3

    公开(公告)日：2017-08-17

    申请号：PCT/IB2016002012

    申请日：2016-12-30

    Applicant: BITFURY GROUP LTD ,  VAVILOVS VALERIJS

    Inventor： NEBESNYI VALERII

    IPC: G06F17/50 ,  H03K3/356

    CPC classification number: H01L27/11807 ,  G06F17/5009 ,  G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F2217/12 ,  H01L2027/11887

    Abstract: Layouts of transmission gates and related techniques and systems are described. An integrated circuit may include first and second transmission gates (150, 160) disposed in a column, and metal wires (174a, 174b, 188a). The first transmission gate (150) includes first and second control terminals (112, 122), and the second transmission gate (160) includes first and second control terminals (132, 142). The metal wires extend between the first and second transmission gates in a direction substantially orthogonal to the column, and include a first control wire (104) coupled to the first control terminals of the first and second transmission gates.

    Abstract translation: 描述了传输门和相关技术和系统的布局。 集成电路可以包括设置在列中的第一和第二传输门（150,160）以及金属线（174a，174b，188a）。 第一传输门（150）包括第一和第二控制终端（112,122），并且第二传输门（160）包括第一和第二控制终端（132,142）。 金属线在基本垂直于该列的方向上在第一和第二传输门之间延伸，并且包括耦合到第一和第二传输门的第一控制端的第一控制线（104）。

Patent Agency Ranking