Invention Grant
- Patent Title: Dual mode memory array security apparatus, systems and methods
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Application No.: US14794560Application Date: 2015-07-08
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Publication No.: US10068631B2Publication Date: 2018-09-04
- Inventor: Chiraag Juvekar , Joyce Kwong , Clive Bittlestone , Srinath Ramaswamy
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Gregory J. Albin; Charles A. Brill; Frank D. Cimino
- Main IPC: G06F21/00
- IPC: G06F21/00 ; G11C11/22 ; H04L9/08 ; H01L27/11507

Abstract:
Read-only (“RO”) data consisting of a physically unclonable function (“PUF”) pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking. The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking. Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.
Public/Granted literature
- US20170011790A1 DUAL MODE MEMORY ARRAY SECURITY APPARATUS, SYSTEMS AND METHODS Public/Granted day:2017-01-12
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