Invention Grant
- Patent Title: Semiconductor memory device for calibrating a termination resistance and a method of calibrating the termination resistance thereof
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Application No.: US15594107Application Date: 2017-05-12
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Publication No.: US10069495B2Publication Date: 2018-09-04
- Inventor: Hangi Jung , Hun-Dae Choi , Jinhyeok Baek
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2016-0076702 20160620
- Main IPC: H03K17/16
- IPC: H03K17/16 ; H03K19/003 ; H03K19/00 ; G11C11/4074 ; G11C11/4099 ; G11C11/4093 ; G11C29/02 ; G11C29/50 ; G11C11/4076 ; G11C11/408
Abstract:
A memory device includes a first on-die termination circuit, a second on-die termination circuit, a voltage generator, and a code generator. The first on-die termination circuit may correspond to a data input buffer. The second on-die termination circuit may correspond to a command/address buffer. The voltage generator may generate a reference voltage. The code generator may generate a resistance calibration code of a selected one of the on-die termination circuits in response to the reference voltage. The reference calibration code may calibrate a resistance value of the selected on-die termination circuit.
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