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    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME 审中-公开

    公开(公告)号：US20200027498A1

    公开(公告)日：2020-01-23

    申请号：US16248004

    申请日：2019-01-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju Ho Jeon ,  Hun-Dae Choi

    IPC: G11C11/4093 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4096 ,  H03K19/00

    Abstract: The semiconductor memory device including a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal, a data input buffer configured to receive data delayed by a first delay time compared to the data strobe signal and generate input data, a latency control signal generator configured to generate and activate a first on-die termination control signal during a first period in which the data strobe signal is applied in response to receiving a write command, a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal, and a data strobe signal termination circuit configured to terminate the data strobe signal and including a first on-die termination resistor, a resistance value of which varies in response to the first variable resistance code may be provided.

    Delay locked loop to cancel offset and memory device including the same
    2.
    发明授权
    Delay locked loop to cancel offset and memory device including the same 有权

    公开(公告)号：US10530371B2

    公开(公告)日：2020-01-07

    申请号：US16376444

    申请日：2019-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Juho Jeon ,  Hun-Dae Choi

    IPC: H03L7/081 ,  G11C29/02 ,  H03L7/087 ,  H03L7/197 ,  H03L7/22 ,  G11C7/10 ,  G11C7/22 ,  H03L7/10

    Abstract: A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.

    MEMORY DEVICE HAVING COMMAND WINDOW GENERATOR
    8.
    发明申请
    MEMORY DEVICE HAVING COMMAND WINDOW GENERATOR 有权

    公开(公告)号：US20180012638A1

    公开(公告)日：2018-01-11

    申请号：US15606963

    申请日：2017-05-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SUKYONG KANG ,  Hun-Dae Choi

    IPC: G11C7/22

    CPC classification number: G11C7/222 ,  G11C7/225 ,  G11C7/227 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2272

    Abstract: A memory device including a command window generator is provided. The command window generator is configured to generate a delay signal by converting a delay time between a clock signal input to a write path circuit and a clock signal output to a write path replica circuit into a number of cycles of an internal clock signal, by using the write path circuit and the write path replica circuit, and generate a command window to correspond to a data window using the delay signal. The delay window may correspond to a burst length of write data.

    Semiconductor memory device and operating method of semiconductor memory device
    9.
    发明授权
    Semiconductor memory device and operating method of semiconductor memory device 有权

    公开(公告)号：US10861516B2

    公开(公告)日：2020-12-08

    申请号：US16357671

    申请日：2019-03-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hun-Dae Choi ,  Hwapyong Kim

    IPC: G11C7/22 ,  G11C8/06 ,  G11C7/06 ,  G11C8/10 ,  G11C7/10

    Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.

    Delay-locked loop circuit, semiconductor memory device, and methods of operating delay-locked loop circuit
    10.
    发明授权
    Delay-locked loop circuit, semiconductor memory device, and methods of operating delay-locked loop circuit 有权

    公开(公告)号：US10727826B2

    公开(公告)日：2020-07-28

    申请号：US16282870

    申请日：2019-02-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hun-Dae Choi ,  Hwa-Pyong Kim

    IPC: H03K5/156 ,  G11C11/4076 ,  H03L7/081 ,  H03L7/089 ,  H03L7/08 ,  G11C11/4093

    Abstract: A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.

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