Methods of fabricating tamper-respondent assemblies are provided which include an electronic enclosure, a tamper-respondent electronic circuit structure, and at least one security element. The electronic enclosure encloses, at least in part, at least one electronic component to be protected, and includes an inner surface. The tamper-respondent electronic circuit structure includes a tamper-respondent sensor covering, at least in part, the inner surface of the electronic enclosure, and the at least one security element overlies and physically secures in place, at least in part, the tamper-respondent sensor covering, at least in part, the inner surface of the electronic enclosure. In enhanced embodiments, the electronic enclosure is secured to a multilayer circuit board which includes an embedded tamper-respondent sensor, and together, the tamper-respondent sensor covering the inner surface of the electronic enclosure and the embedded tamper-respondent sensor within the multilayer circuit board define a secure volume about the electronic component(s).