Invention Grant
- Patent Title: Delayed data release after programming to reduce read errors in memory
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Application No.: US15408943Application Date: 2017-01-18
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Publication No.: US10255000B2Publication Date: 2019-04-09
- Inventor: Sahil Sharma , Philip Reusswig , Nian Niles Yang , Rohit Sehgal , Gautham Reddy
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vierra Magen Marcus LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G11C16/28 ; G11C16/10 ; G11C11/56 ; G11C16/16 ; G11C16/34 ; G11C16/04

Abstract:
A memory device and associated techniques avoid reading memory cells immediately after programming when uncorrectable errors may be present. In one aspect, data is copied from one block to another block and a timer is started after the copying is completed. If a read command is received before the timer has expired, the read operation proceeds by reading the one block. If the read command is received after the timer has expired, the read operation proceeds by reading the another block. This approach is particular suitable when data is copied from single-level cell (SLC) blocks to multi-level cell (MLC) blocks in a folding operation. The duration of the timer can be increased at lower temperatures.
Public/Granted literature
- US20180203642A1 Delayed Data Release After Programming To Reduce Read Errors In Memory Public/Granted day:2018-07-19
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