公开(公告)号：US11935609B2

公开(公告)日：2024-03-19

申请号：US17743287

申请日：2022-05-12

Applicant: Western Digital Technologies, Inc.

Inventor： Oleg Kragel ,  Vijay Sivasankaran ,  Man Lung Mui ,  Sahil Sharma

IPC: G11C7/00 ,  G11C7/10 ,  G11C29/12 ,  G11C29/42 ,  H03K19/21

CPC classification number: G11C29/42 ,  G11C7/1039 ,  G11C29/1201 ,  H03K19/21 ,  G11C2029/1202

Abstract: Embodiments described herein provide a linked XOR flash data protection scheme for data storage devices. In particular, the embodiments described herein provide a data storage controller with a memory space efficient XOR-based flash data protection/recovery algorithm with minimal flash block space overhead and support of recovery from full plane failure with neighbor planes disturb (NPD) in a single word line. Additionally, the embodiments described herein provide a reduced flash block space dedicated for XOR parity buffers storage by a factor of a number of planes per die without losing the capability to recover from NPD.

公开(公告)号：US11385984B2

公开(公告)日：2022-07-12

申请号：US16798650

申请日：2020-02-24

Applicant: Western Digital Technologies, Inc.

Inventor： Nian Yang ,  Piyush Dhotre ,  Sahil Sharma

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/10 ,  G06F9/48 ,  G06F11/14 ,  G06F1/20 ,  G06F12/0882

Abstract: A method and apparatus for dynamically determining when, or how often, to do a read scan operation on a solid-state storage drive. One solution adjusts a read scan interval as part of performing a read scan operation. First, a bit error rate is determined for one of a plurality of storage blocks of a non-volatile memory array. Then, a cross temperature metric for the storage block is determined. A read scan interval is changed in response to the cross temperature metric satisfying a cross temperature threshold. Then, data in the storage block is relocated to a free storage block in response to the bit error rate satisfying a relocation threshold.

公开(公告)号：US11354190B2

公开(公告)日：2022-06-07

申请号：US17184422

申请日：2021-02-24

Applicant: Western Digital Technologies, Inc.

Inventor： Rohit Sehgal ,  Sahil Sharma ,  Nian Niles Yang ,  Philip David Reusswig

IPC: G06F11/10 ,  G06F11/07 ,  G06F12/02 ,  G06F11/14

Abstract: Methods and apparatus for storing parity bits in an available over provisioning (OP) space to recover data lost from an entire memory block. For example, a data storage device may receive data from a host device, write the data to a block, and generate a corresponding block parity. The device may then determine a bit error rate (BER) of the block and an average programming duration to write the data written to the block, calculate a probability of the block becoming defective based on the BER and the average programming duration, and comparing the probability of the block to a set of probabilities respectively corresponding to a set of worst-performing blocks in a NVM. Thereafter, the device may write the block parity to an available over provisioning (OP) space in the NVM responsive to the probability of the block being greater than any probability in the set of probabilities.

公开(公告)号：US20210240358A1

公开(公告)日：2021-08-05

申请号：US16780281

申请日：2020-02-03

Applicant: Western Digital Technologies, Inc.

Inventor： Sahil Sharma ,  Nian Niles Yang ,  Phil Reusswig ,  Rohit Sehgal ,  Piyush A. Dhotre

IPC: G06F3/06 ,  G11C11/408 ,  G06F11/07 ,  G11C11/409

Abstract: A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.

公开(公告)号：US10971215B1

公开(公告)日：2021-04-06

申请号：US16798590

申请日：2020-02-24

Applicant: Western Digital Technologies, Inc.

Inventor： Nian Yang ,  Sahil Sharma ,  Piyush Dhotre

IPC: G11C11/56 ,  G11C11/4096 ,  G11C11/4076 ,  G11C29/42 ,  G11C29/44 ,  G11C29/46 ,  G11C7/22

Abstract: A circuit configured to dynamically adjust data transfer speeds for a non-volatile memory die interface. The circuit includes an initialization circuit, a control circuit, a switch circuit, and a read-write circuit. The initialization circuit is configured to load multi-level cell settings that configure a memory interface for transfer of data for storage cells configured to store more than one bit per storage cell. The control circuit is configured to receive a read command that references single-level storage cells of a memory die. The switch circuit is configured to switch settings for the memory interface from the multi-level cell settings to single level cell settings, in response to receiving the read command. The read-write circuit is configured to read data for the read command from the memory die using the single level cell settings.

公开(公告)号：US10832784B2

公开(公告)日：2020-11-10

申请号：US16862436

申请日：2020-04-29

Applicant: Western Digital Technologies, Inc.

Inventor： Sahil Sharma ,  Nian Yang ,  Philip David Reusswig

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/04

Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.

公开(公告)号：US10732864B2

公开(公告)日：2020-08-04

申请号：US15666877

申请日：2017-08-02

Applicant: Western Digital Technologies, Inc.

Inventor： Sahil Sharma

IPC: G06F3/06

Abstract: A data storage device includes a power input port, a nonvolatile memory module, a controller for the nonvolatile memory module, and a power analyzer electrically coupled to the power input port. The power analyzer is configured to receive input power from the power input port, determine power data associated with the data storage device based on the input power, and store the power data in a memory of the power analyzer.

公开(公告)号：US10255000B2

公开(公告)日：2019-04-09

申请号：US15408943

申请日：2017-01-18

Applicant: Western Digital Technologies, Inc.

Inventor： Sahil Sharma ,  Philip Reusswig ,  Nian Niles Yang ,  Rohit Sehgal ,  Gautham Reddy

IPC: G06F3/06 ,  G11C16/28 ,  G11C16/10 ,  G11C11/56 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: A memory device and associated techniques avoid reading memory cells immediately after programming when uncorrectable errors may be present. In one aspect, data is copied from one block to another block and a timer is started after the copying is completed. If a read command is received before the timer has expired, the read operation proceeds by reading the one block. If the read command is received after the timer has expired, the read operation proceeds by reading the another block. This approach is particular suitable when data is copied from single-level cell (SLC) blocks to multi-level cell (MLC) blocks in a folding operation. The duration of the timer can be increased at lower temperatures.

公开(公告)号：US11941269B2

公开(公告)日：2024-03-26

申请号：US17701348

申请日：2022-03-22

Applicant: Western Digital Technologies, Inc.

Inventor： Niles Yang ,  Sahil Sharma ,  Phil D. Reusswig

IPC: G06F3/06 ,  G06F1/3206

CPC classification number: G06F3/0634 ,  G06F1/3206 ,  G06F3/0625 ,  G06F3/0679

Abstract: A data storage device includes a non-volatile memory device having one or more memory dies and each of the memory dies include a plurality of input-output (I/O) lines. The data storage device further includes a controller. The controller is configured to receive an instruction to enter a low-power operating mode. Entering the low-power operating mode includes removing power from the one or more memory dies, providing an output signal toggling between a logic high and a logic low at a predetermined frequency to the plurality of I/O lines for a predetermined period of time, and operating in the low-power operating mode upon the expiration of the predetermined period of time.

公开(公告)号：US20230368857A1

公开(公告)日：2023-11-16

申请号：US17743287

申请日：2022-05-12

Applicant: Western Digital Technologies, Inc.

Inventor： Oleg Kragel ,  Vijay Sivasankaran ,  Man Lung Mui ,  Sahil Sharma

IPC: G11C29/42 ,  G11C29/12 ,  G11C7/10 ,  H03K19/21

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C7/1039 ,  H03K19/21 ,  G11C2029/1202

Abstract: Embodiments described herein provide a linked XOR flash data protection scheme for data storage devices. In particular, the embodiments described herein provide a data storage controller with a memory space efficient XOR-based flash data protection/recovery algorithm with minimal flash block space overhead and support of recovery from full plane failure with neighbor planes disturb (NPD) in a single word line. Additionally, the embodiments described herein provide a reduced flash block space dedicated for XOR parity buffers storage by a factor of a number of planes per die without losing the capability to recover from NPD.