- Patent Title: Vertical thyristor memory with minority carrier lifetime reduction
-
Application No.: US15426972Application Date: 2017-02-07
-
Publication No.: US10256241B2Publication Date: 2019-04-09
- Inventor: Harry Luan , Valery Axelrad , Charlie Cheng
- Applicant: TC Lab, Inc.
- Applicant Address: US CA Gilroy
- Assignee: TC Lab, Inc.
- Current Assignee: TC Lab, Inc.
- Current Assignee Address: US CA Gilroy
- Agency: Aka Chan LLP
- Main IPC: H01L29/74
- IPC: H01L29/74 ; H01L31/111 ; H01L27/102 ; H01L21/285 ; H01L21/8229 ; H01L23/532 ; H01L29/45 ; H01L21/02 ; H01L21/22 ; H01L21/3205 ; H01L27/108 ; H01L29/06 ; H01L29/16 ; H01L29/66 ; H01L21/265 ; H01L29/161 ; G11C11/39 ; H01L27/08 ; H01L29/08 ; H01L29/87 ; H01L49/02 ; H01L29/165

Abstract:
Apparatus and methods for reducing minority carriers in a memory array are described herein. Minority carriers diffuse between ON cells and OFF cells, causing disturbances during write operation as well as reducing the retention lifetime of the cells. Minority Carrier Lifetime Killer (MCLK) region architectures are described for vertical thyristor memory arrays with insulation trenches. These MCLK regions encourage recombination of minority carriers. In particular, MCLK regions formed by conductors embedded along the cathode line of a thyristor array, as well as dopant MCLK regions are described, as well as methods for manufacturing thyristor memory cells with MCLK regions.
Public/Granted literature
- US20170229306A1 Vertical Thyristor Memory with Minority Carrier Lifetime Reduction Public/Granted day:2017-08-10
Information query
IPC分类: