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    Formation of Stacked Lateral Semiconductor Devices and the Resulting Structures
    1.
    发明申请
    Formation of Stacked Lateral Semiconductor Devices and the Resulting Structures 有权

    公开(公告)号：US20210233767A1

    公开(公告)日：2021-07-29

    申请号：US17229655

    申请日：2021-04-13

    Applicant: TC Lab, Inc.

    Inventor： Harry Luan

    IPC: H01L21/02 ,  H01L29/74

    Abstract: A method of making stacked lateral semiconductor devices is disclosed. The method includes depositing a stack of alternating layers of different materials. Slots or holes are cut through the layers for subsequent formation of single crystal semiconductor fences or pillars. When each of the alternating layers of one material are removed space is provided for formation of single crystal semiconductor devices between the remaining layers. The devices are doped as the single crystal silicon is formed.

    Multi-Layer Horizontal Thyristor Random Access Memory and Peripheral Circuitry
    2.
    发明申请
    Multi-Layer Horizontal Thyristor Random Access Memory and Peripheral Circuitry 有权

    公开(公告)号：US20210217753A1

    公开(公告)日：2021-07-15

    申请号：US17218020

    申请日：2021-03-30

    Applicant: TC Lab, Inc.

    Inventor： Harry Luan

    IPC: H01L27/108 ,  H01L29/74 ,  H01L29/66 ,  H01L23/535 ,  H01L21/02

    Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

    Multi-Layer Random Access Memory and Methods of Manufacture
    3.
    发明申请
    Multi-Layer Random Access Memory and Methods of Manufacture 审中-公开

    公开(公告)号：US20200381434A1

    公开(公告)日：2020-12-03

    申请号：US16996838

    申请日：2020-08-18

    Applicant: TC Lab, Inc.

    Inventor： Harry Luan

    IPC: H01L27/102 ,  H01L29/74 ,  H01L21/311 ,  H01L21/02 ,  H01L27/108 ,  H01L29/66 ,  H01L23/528

    Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

    High-speed data transfer periods for thyristor memory cell arrays
    6.
    发明授权
    High-speed data transfer periods for thyristor memory cell arrays 有权

    公开(公告)号：US10553269B2

    公开(公告)日：2020-02-04

    申请号：US16124133

    申请日：2018-09-06

    Applicant: TC Lab, Inc.

    Inventor： Bruce L. Bateman

    IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00

    Abstract: Aspects of DDR and thyristor memory cell RAMs are optimally combined for high-speed data transfer into and out of RAMs. After a Read operation in which data from a selected row of memory cells in an array are latched, a Burst operation selectively moves the latched data from the array or latches external data. At the same time as the Burst data transfer, all the memory cells of the selected row are turned off or on by a write operation. In the following Write-Back & Pre-charge operation, the latched data bits which are complementary to the memory cell state of the Burst write operation are written back into the corresponding memory cells in the selected row. As part of a DDR-like activation cycle, data can be transferred to and from the memory cell array RAM at high-speed.

    3D memory array clusters and resulting memory architecture
    8.
    发明授权
    3D memory array clusters and resulting memory architecture 有权

    公开(公告)号：US11133049B2

    公开(公告)日：2021-09-28

    申请号：US16226554

    申请日：2018-12-19

    Applicant: TC Lab, Inc.

    Inventor： Bruce L. Bateman

    IPC: G11C11/39 ,  G11C5/02 ,  G11C7/06 ,  G11C7/18 ,  G11C7/12 ,  G11C5/06

    Abstract: A memory architecture for 3-dimensional thyristor cell arrays is disclosed. Thyristor memory cells are connected in a 3-dimensional cross-point array to form a bit line cluster. The bit line clusters are connected in parallel to sense amplifier and write circuits through multiplexer/demultiplexer circuits. Control circuits select one of the bit line clusters during a read or write operation while the non-selected bit line clusters are not activated to avoid disturbs and power consumption in the non-selected bit line clusters. The bit line clusters, multiplexer/demultiplexer circuits, and sense amplifier and write circuits from a memory array tile (MAT).

    3D Stacked High-Density Memory Cell Arrays and Methods of Manufacture
    9.
    发明申请
    3D Stacked High-Density Memory Cell Arrays and Methods of Manufacture 审中-公开

    公开(公告)号：US20200258562A1

    公开(公告)日：2020-08-13

    申请号：US16861065

    申请日：2020-04-28

    Applicant: TC Lab, Inc.

    Inventor： Harry Luan

    IPC: G11C11/39 ,  H01L29/66 ,  H01L29/06 ,  H01L29/87 ,  H01L27/102 ,  H01L29/74 ,  H01L27/105 ,  H01L27/108

    Abstract: Integrated circuit devices having multiple level arrays of thyristor memory cells are created using a stack of ONO layers through which NPNPNPN layered silicon pillars are epitaxially grown in-situ. Intermediate conducting lines formed in place of the removed nitride layer of the ONO stack contact the middle P-layer of silicon pillars. The silicon pillars form two arrays of thyristor memory cells, one stacked upon the other, having the intermediate conducting lines as common connections to both arrays. The stacked arrays can also be provided with assist-gates.

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