公开(公告)号：US20210233767A1

公开(公告)日：2021-07-29

申请号：US17229655

申请日：2021-04-13

申请人： TC Lab, Inc.

发明人： Harry Luan

IPC分类号： H01L21/02 ,  H01L29/74

摘要： A method of making stacked lateral semiconductor devices is disclosed. The method includes depositing a stack of alternating layers of different materials. Slots or holes are cut through the layers for subsequent formation of single crystal semiconductor fences or pillars. When each of the alternating layers of one material are removed space is provided for formation of single crystal semiconductor devices between the remaining layers. The devices are doped as the single crystal silicon is formed.

公开(公告)号：US20210217753A1

公开(公告)日：2021-07-15

申请号：US17218020

申请日：2021-03-30

申请人： TC Lab, Inc.

发明人： Harry Luan

IPC分类号： H01L27/108 ,  H01L29/74 ,  H01L29/66 ,  H01L23/535 ,  H01L21/02

摘要： A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

公开(公告)号：US20200381434A1

公开(公告)日：2020-12-03

申请号：US16996838

申请日：2020-08-18

申请人： TC Lab, Inc.

发明人： Harry Luan

IPC分类号： H01L27/102 ,  H01L29/74 ,  H01L21/311 ,  H01L21/02 ,  H01L27/108 ,  H01L29/66 ,  H01L23/528

摘要： A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

公开(公告)号：US10700069B2

公开(公告)日：2020-06-30

申请号：US16007992

申请日：2018-06-13

申请人： TC Lab, Inc.

发明人： Harry Luan

IPC分类号： H01L29/66 ,  H01L27/10 ,  H01L21/02 ,  H01L27/108 ,  H01L29/74 ,  H01L29/165 ,  H01L29/10

摘要： A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.

公开(公告)号：US10553588B2

公开(公告)日：2020-02-04

申请号：US16015164

申请日：2018-06-21

申请人： TC Lab, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： G11C19/08 ,  H01L27/102 ,  H01L29/749 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L29/45 ,  H01L49/02 ,  G11C11/39 ,  H01L21/28 ,  H01L21/321 ,  H01L29/423 ,  H01L29/08

摘要： Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.

公开(公告)号：US10553269B2

公开(公告)日：2020-02-04

申请号：US16124133

申请日：2018-09-06

申请人： TC Lab, Inc.

发明人： Bruce L. Bateman

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C13/00

摘要： Aspects of DDR and thyristor memory cell RAMs are optimally combined for high-speed data transfer into and out of RAMs. After a Read operation in which data from a selected row of memory cells in an array are latched, a Burst operation selectively moves the latched data from the array or latches external data. At the same time as the Burst data transfer, all the memory cells of the selected row are turned off or on by a write operation. In the following Write-Back & Pre-charge operation, the latched data bits which are complementary to the memory cell state of the Burst write operation are written back into the corresponding memory cells in the selected row. As part of a DDR-like activation cycle, data can be transferred to and from the memory cell array RAM at high-speed.

公开(公告)号：US11763872B2

公开(公告)日：2023-09-19

申请号：US17488148

申请日：2021-09-28

申请人： TC Lab, Inc.

发明人： Bruce L. Bateman

IPC分类号： G11C11/39 ,  G11C5/02 ,  G11C7/06 ,  G11C7/18 ,  G11C7/12 ,  G11C5/06

CPC分类号： G11C11/39 ,  G11C5/025 ,  G11C5/063 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18

摘要： A memory architecture for 3-dimensional thyristor cell arrays is disclosed. Thyristor memory cells are connected in a 3-dimensional cross-point array to form a bit line cluster. The bit line clusters are connected in parallel to sense amplifier and write circuits through multiplexer/demultiplexer circuits. Control circuits select one of the bit line clusters during a read or write operation while the non-selected bit line clusters are not activated to avoid disturbs and power consumption in the non-selected bit line clusters. The bit line clusters, multiplexer/demultiplexer circuits, and sense amplifier and write circuits from a memory array tile (MAT).

公开(公告)号：US11114438B2

公开(公告)日：2021-09-07

申请号：US17090742

申请日：2020-11-05

申请人： TC Lab, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L27/102 ,  H01L29/749 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L29/45 ,  H01L49/02 ,  G11C11/39 ,  H01L21/28 ,  H01L21/321 ,  H01L29/423 ,  H01L29/08

摘要： A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

公开(公告)号：US10978456B2

公开(公告)日：2021-04-13

申请号：US16914181

申请日：2020-06-26

申请人： TC Lab, Inc.

发明人： Harry Luan

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L29/74 ,  H01L29/165 ,  H01L29/10 ,  H01L29/66

摘要： A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.

公开(公告)号：US20190378554A1

公开(公告)日：2019-12-12

申请号：US16124133

申请日：2018-09-06

申请人： TC Lab, Inc.

发明人： Bruce L. Bateman

IPC分类号： G11C11/16 ,  G11C13/00

摘要： Aspects of DDR and thyristor memory cell RAMs are optimally combined for high-speed data transfer into and out of RAMs. After a Read operation in which data from a selected row of memory cells in an array are latched, a Burst operation selectively moves the latched data from the array or latches external data. At the same time as the Burst data transfer, all the memory cells of the selected row are turned off or on by a write operation. In the following Write-Back & Pre-charge operation, the latched data bits which are complementary to the memory cell state of the Burst write operation are written back into the corresponding memory cells in the selected row. As part of a DDR-like activation cycle, data can be transferred to and from the memory cell array RAM at high-speed.