- 专利标题： Determining bias configuration for write operations in memory to improve device performance during normal operation as well as to improve the effectiveness of testing routines
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申请号： US15401235申请日： 2017-01-09
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公开(公告)号： US10262713B2公开(公告)日： 2019-04-16
- 发明人: Jason Janesky , Syed M. Alam , Dimitri Houssameddine , Mark Deherrera
- 申请人： Everspin Technologies, Inc.
- 申请人地址： US AZ Chandler
- 专利权人： Everspin Technologies, Inc.
- 当前专利权人： Everspin Technologies, Inc.
- 当前专利权人地址： US AZ Chandler
- 代理机构： Bookoff McAndrews, PLLC
- 主分类号： G11C11/56
- IPC分类号： G11C11/56 ; G11C11/16 ; G11C29/12 ; G11C29/02 ; G11C29/50 ; G11C17/16
摘要：
Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.
公开/授权文献
- US20170117029A1 BIAS CONFIGURATION FOR WRITE OPERATIONS IN MEMORY 公开/授权日：2017-04-27
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