公开(公告)号：US10923170B2

公开(公告)日：2021-02-16

申请号：US16358414

申请日：2019-03-19

Applicant: Everspin Technologies, Inc.

Inventor： Jason Janesky ,  Syed M. Alam ,  Dimitri Houssameddine ,  Mark Deherrera

IPC: G11C11/16 ,  G11C29/12 ,  G11C29/02 ,  G11C29/50 ,  G11C17/16

Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.

公开(公告)号：US10230046B2

公开(公告)日：2019-03-12

申请号：US15856202

申请日：2017-12-28

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Kerry Nagel ,  Jason Janesky

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

公开(公告)号：US09954163B2

公开(公告)日：2018-04-24

申请号：US14712130

申请日：2015-05-14

Applicant: Everspin Technologies, Inc.

Inventor： Wenchin Lin ,  Jason Janesky

IPC: H01L29/82 ,  H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L23/14 ,  G11C5/00 ,  H01L23/552 ,  G11C11/16 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01L43/02 ,  G11C5/005 ,  G11C11/16 ,  H01L23/13 ,  H01L23/14 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L27/222 ,  H01L43/12 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/1441 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.

公开(公告)号：US10600460B2

公开(公告)日：2020-03-24

申请号：US16157315

申请日：2018-10-11

Applicant: Everspin Technologies, Inc.

Inventor： Sarin Deshpande ,  Sanjeev Aggarwal ,  Jason Janesky ,  Jon Slaughter ,  Phillip Lopresti

IPC: G11C11/16 ,  H01F10/32 ,  H01L27/22 ,  H01L43/02

Abstract: Spin-orbit-torque (SOT) control strip lines are provided along the sides of free layers in perpendicular magnetic tunnel junction devices. Current flowing through such SOT control strip lines injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used to force the magnetic state of the free layer to a particular state based on the direction of the current through the SOT control strip line. In other embodiments, the SOT provides an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction. Some embodiments have dedicated strip lines for a single magnetic tunnel junction such that a three-terminal device results. Other embodiments have multiple magnetic tunnel junctions sharing a strip line, where the strip line can be used to reset all of the magnetic tunnel junctions to the same state and can also be used as an assist such that individual magnetic tunnel junctions can be written using selection circuitry.

公开(公告)号：US09893275B2

公开(公告)日：2018-02-13

申请号：US15396700

申请日：2017-01-02

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Kerry Nagel ,  Jason Janesky

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.

公开(公告)号：US09093640B2

公开(公告)日：2015-07-28

申请号：US14219902

申请日：2014-03-19

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Kerry Nagel ,  Jason Janesky

IPC: H01L43/12

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.

Abstract translation: 双隧道屏障磁性元件具有位于第一和第二隧道屏障之间的自由磁性层和位于第二隧道屏障上的电极。 两步蚀刻工艺允许在第一次蚀刻之后在电极的侧壁上形成封装材料，并且在进行第二蚀刻以去除自由层的一部分时防止第一隧道势垒的损坏。

公开(公告)号：US20200185602A1

公开(公告)日：2020-06-11

申请号：US16794449

申请日：2020-02-19

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry NAGEL ,  Jason Janesky

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

公开(公告)号：US20190157550A1

公开(公告)日：2019-05-23

申请号：US16255912

申请日：2019-01-24

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry NAGEL ,  Jason Janesky

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

公开(公告)号：US09543041B2

公开(公告)日：2017-01-10

申请号：US14837381

申请日：2015-08-27

Applicant: Everspin Technologies, Inc.

Inventor： Jason Janesky ,  Syed M. Alam ,  Dimitri Houssameddine ,  Mark Deherrera

IPC: G11C11/34 ,  G11C11/00 ,  G11C29/12 ,  G11C29/02 ,  G11C29/50 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/16 ,  G11C11/1675 ,  G11C17/16 ,  G11C29/021 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/12 ,  G11C29/50

Abstract: Techniques and circuits for testing and configuring magnetic memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation. Examples include adjustment of bias voltages, sense amplifier offset values, and timing parameters to improve the efficiency of testing operations as well as improve reliability and speed of normal operation.

Abstract translation: 介绍了用于测试和配置磁存储器件的技术和电路。 寄存器和非易失性存储器包含在存储器件中，用于存储用于控制存储器件测试的值以及用于配置与测试和正常操作相关的参数。 示例包括偏置电压的调整，读出放大器偏移值和定时参数，以提高测试操作的效率，以及提高正常操作的可靠性和速度。

公开(公告)号：US20160172582A1

公开(公告)日：2016-06-16

申请号：US15043633

申请日：2016-02-15

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jason Janesky ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22

CPC classification number: H01L43/02 ,  B82Y10/00 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  Y10S977/935

Abstract: A magnetoresistive memory array including a plurality of magnetoresistive memory elements wherein each magnetoresistive memory element comprises a free layer including at least one ferromagnetic layer having perpendicular magnetic anisotropy, a fixed layer, and a tunnel barrier, disposed between and in contact with the free and fixed layers. The tunnel barrier includes a first metal-oxide layer, having a thickness between 1 and 10 Angstroms, a second metal-oxide layer, having a thickness between 3 and 6 Angstroms, disposed on the first metal-oxide layer, and a third metal-oxide layer, having a thickness between 3 and 6 Angstroms, disposed over the second metal-oxide layer. In one embodiment, the third metal-oxide layer is in contact with the free layer or fixed layer. The tunnel barrier may also include a fourth metal-oxide layer, having a thickness between 1 and 10 Angstroms, disposed between the second and third metal-oxide layers.

Abstract translation: 一种包括多个磁阻存储元件的磁阻存储器阵列，其中每个磁阻存储元件包括自由层，该自由层包括至少一个具有垂直磁各向异性的铁磁层，固定层和隧道势垒，该自由层设置在自由和固定 层。 隧道势垒包括设置在第一金属氧化物层上的第一金属氧化物层，其厚度为1至10埃，厚度为3埃至6埃的第二金属氧化物层，以及第三金属氧化物层， 氧化物层，其厚度为3埃至6埃，设置在第二金属氧化物层上。 在一个实施例中，第三金属氧化物层与自由层或固定层接触。 隧道势垒还可以包括设置在第二和第三金属氧化物层之间的厚度在1埃和10埃之间的第四金属氧化物层。