- Patent Title: Determining bias configuration for write operations in memory to improve device performance during normal operation as well as to improve the effectiveness of testing routines
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Application No.: US15401235Application Date: 2017-01-09
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Publication No.: US10262713B2Publication Date: 2019-04-16
- Inventor: Jason Janesky , Syed M. Alam , Dimitri Houssameddine , Mark Deherrera
- Applicant: Everspin Technologies, Inc.
- Applicant Address: US AZ Chandler
- Assignee: Everspin Technologies, Inc.
- Current Assignee: Everspin Technologies, Inc.
- Current Assignee Address: US AZ Chandler
- Agency: Bookoff McAndrews, PLLC
- Main IPC: G11C11/56
- IPC: G11C11/56 ; G11C11/16 ; G11C29/12 ; G11C29/02 ; G11C29/50 ; G11C17/16
Abstract:
Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.
Public/Granted literature
- US20170117029A1 BIAS CONFIGURATION FOR WRITE OPERATIONS IN MEMORY Public/Granted day:2017-04-27
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