Invention Grant
- Patent Title: Internal spacer formation for nanowire semiconductor devices
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Application No.: US15822497Application Date: 2017-11-27
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Publication No.: US10269929B2Publication Date: 2019-04-23
- Inventor: Kurt Wostyn , Liesbeth Witters , Hans Mertens
- Applicant: IMEC VZW
- Applicant Address: BE Leuven
- Assignee: IMEC VZW
- Current Assignee: IMEC VZW
- Current Assignee Address: BE Leuven
- Agency: McDonnell Boehnen Hulbert & Berghoff LLP
- Priority: EP16203209 20161209
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L21/02 ; H01L21/311 ; H01L29/423 ; H01L29/08 ; H01L29/16 ; B82Y10/00 ; H01L29/417 ; H01L29/775 ; H01L29/786

Abstract:
The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.
Public/Granted literature
- US20180166558A1 Internal Spacer Formation for Nanowire Semiconductor Devices Public/Granted day:2018-06-14
Information query
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