中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.013 seconds)

    Integration of Semiconductor Structures
    1.
    发明申请
    Integration of Semiconductor Structures 审中-公开

    公开(公告)号：US20180286762A1

    公开(公告)日：2018-10-04

    申请号：US15913546

    申请日：2018-03-06

    Applicant: IMEC VZW

    Inventor： Kurt Wostyn

    IPC: H01L21/8234 ,  H01L21/225 ,  H01L27/088

    Abstract: At least one embodiment relates to a method for integrating Si1-xGex structures with Si1-x′Gex′ structures in a semiconductor device. The method includes providing a device that includes a plurality of Si1-xGex structures, where 0≤x x.

    Counteracting Semiconductor Material Loss During Semiconductor Structure Formation
    2.
    发明申请
    Counteracting Semiconductor Material Loss During Semiconductor Structure Formation 有权

    公开(公告)号：US20210351275A1

    公开(公告)日：2021-11-11

    申请号：US17308453

    申请日：2021-05-05

    Applicant: IMEC VZW

    Inventor： Kurt Wostyn ,  Yusuke Oniki ,  Hans Mertens

    IPC: H01L29/423 ,  H01L29/786 ,  H01L21/311 ,  H01L29/66

    Abstract: Example embodiments relate to counteracting semiconductor material loss during semiconductor structure formation. One embodiment includes a method for forming a semiconductor structure. The method includes providing a structure. The structure includes a substrate. The structure also includes a layer stack on the substrate. The layer stack includes at least one semiconductor layer of a semiconductor material and at least one sacrificial layer under the semiconductor layer. Further, the structure includes a trench through the layer stack. The further also includes forming a recess in the layer stack by etching a portion of the sacrificial layer exposed by the trench. The etching includes a preferential etch of the sacrificial layer with respect to the semiconductor layer. Additionally, the method includes epitaxially growing a liner of the semiconductor material onto surfaces of the semiconductor layer exposed by the trench.

    Horizontal nanowire semiconductor devices
    4.
    发明授权
    Horizontal nanowire semiconductor devices 有权

    公开(公告)号：US10468483B2

    公开(公告)日：2019-11-05

    申请号：US15822478

    申请日：2017-11-27

    Applicant: IMEC VZW

    Inventor： Kurt Wostyn ,  Hans Mertens

    IPC: H01L29/06 ,  H01L21/306 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02

    Abstract: The present disclosure relates to a method of forming a semiconductor device comprising horizontal nanowires. The method comprises depositing a multilayer stack on a substrate, the multilayer stack comprising first sacrificial layers alternated with layers of nanowire material; forming at least one fin in the multilayer stack; applying an additional sacrificial layer around the fin such that a resulting sacrificial layer is formed all around the nanowire material; and forming a nanowire spacer, starting from the resulting sacrificial layer, around the nanowire material at an extremity of the nanowire material. The present disclosure also relates to a corresponding semiconductor device.

    SEMICONDUCTOR DEVICES COMPRISING MULTIPLE CHANNELS AND METHOD OF MAKING SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES COMPRISING MULTIPLE CHANNELS AND METHOD OF MAKING SAME 有权
    包含多个通道的半导体器件及其制造方法

    公开(公告)号：US20170025314A1

    公开(公告)日：2017-01-26

    申请号：US15199535

    申请日：2016-06-30

    Applicant: IMEC VZW

    Inventor： Liesbeth Witters ,  Kurt Wostyn

    IPC: H01L21/8238 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423

    CPC classification number: H01L21/823807 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3065 ,  H01L21/823412 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7849 ,  H01L29/78696

    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a method of fabricating a transistor device comprises forming on the substrate a plurality of vertically repeating layer stacks each comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration compared to the other two of the first, second and third layers. The method additionally includes selectively removing the first layer with respect to the second and third layers from each of the layer stacks, such that a gap interposed between the second layer and the third layer is formed in each of the layer stacks. The method further includes selectively removing the second layer from each of the layer stacks with respect to the third layer, wherein removing the second layer comprises at least partially removing the second layer through the gap, thereby defining the channels comprising a plurality of vertically arranged third layers.

    Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及包括多个通道的晶体管器件。 一方面，一种制造晶体管器件的方法包括在衬底上形成多个垂直重复的层堆叠，每个堆叠层包括以预定顺序堆叠的第一层，第二层和第三层，其中第一，第二和第 第三层由硅，硅锗或锗形成，并且与第一层，第二层和第三层中的其它两层相比具有不同的锗浓度。 该方法还包括相对于每个层堆叠的第二层和第三层选择性地去除第一层，使得在每个层堆叠中形成插入在第二层和第三层之间的间隙。 所述方法还包括相对于所述第三层从所述层堆叠中选择性地去除所述第二层，其中，去除所述第二层包括通过所述间隙至少部分地移除所述第二层，从而限定所述通道，所述通道包括多个垂直布置的第三层 层。

    STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
    7.
    发明申请
    STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME 审中-公开

    公开(公告)号：US20200176583A1

    公开(公告)日：2020-06-04

    申请号：US16696841

    申请日：2019-11-26

    Applicant: IMEC vzw

    Inventor： Kurt Wostyn

    IPC: H01L29/66 ,  H01L29/161 ,  H01L29/08 ,  H01L29/06

    Abstract: This disclosed technology generally relates to a semiconductor device. One aspect relates to a method of fabricating a stacked semiconductor including forming a semiconductor structure protruding above the substrate and a gate structure extending across the semiconductor structure. The semiconductor structure includes a lower channel layer formed of a first material, an intermediate layer formed of a second material and an upper channel layer formed of a third material. The method additionally includes forming oxidized end portions defining second spacers on end surfaces of an upper layer. And forming the oxidized end portions comprises oxidizing end portions of the upper channel layer at opposite sides of the gate structure using an oxidization process adapted to cause a rate of oxidation of the third material which is greater than a rate of oxidation of the first material, while first spacers cover intermediate end surfaces.

    Internal spacers for nanowire semiconductor devices
    8.
    发明授权
    Internal spacers for nanowire semiconductor devices 有权

    公开(公告)号：US10361268B2

    公开(公告)日：2019-07-23

    申请号：US15907878

    申请日：2018-02-28

    Applicant: IMEC VZW

    Inventor： Kurt Wostyn ,  Hans Mertens ,  Liesbeth Witters ,  Andriy Hikavyy ,  Naoto Horiguchi

    IPC: H01L29/06 ,  H01L29/66 ,  B82Y40/00 ,  H01L21/8234 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/775 ,  H01L21/311

    Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

    Internal spacer formation for nanowire semiconductor devices
    9.
    发明授权
    Internal spacer formation for nanowire semiconductor devices 有权

    公开(公告)号：US10269929B2

    公开(公告)日：2019-04-23

    申请号：US15822497

    申请日：2017-11-27

    Applicant: IMEC VZW

    Inventor： Kurt Wostyn ,  Liesbeth Witters ,  Hans Mertens

    IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L29/423 ,  H01L29/08 ,  H01L29/16 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

    Abstract: The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.

Patent Agency Ranking