Invention Grant
- Patent Title: Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
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Application No.: US15167662Application Date: 2016-05-27
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Publication No.: US10297518B2Publication Date: 2019-05-21
- Inventor: Yaojian Lin , Kang Chen , Yu Gu
- Applicant: STATS ChipPAC Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/00 ; H01L21/56 ; H01L23/498 ; H01L21/48 ; H01L23/29

Abstract:
A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer and includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.
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Information query
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