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    Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
    2.
    发明授权
    Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package 有权

    公开(公告)号：US10297518B2

    公开(公告)日：2019-05-21

    申请号：US15167662

    申请日：2016-05-27

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu

    IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/29

    Abstract: A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer and includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.

    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
    3.
    发明授权
    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units 有权

    公开(公告)号：US11024561B2

    公开(公告)日：2021-06-01

    申请号：US16885640

    申请日：2020-05-28

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

    Semiconductor Device and Method of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
    4.
    发明申请
    Semiconductor Device and Method of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units 审中-公开

    公开(公告)号：US20200294890A1

    公开(公告)日：2020-09-17

    申请号：US16885640

    申请日：2020-05-28

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
    5.
    发明授权
    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units 有权

    公开(公告)号：US10707150B2

    公开(公告)日：2020-07-07

    申请号：US16030668

    申请日：2018-07-09

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

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