Invention Grant
- Patent Title: Reconfigurable Ethernet receiver and an analog front-end circuit thereof
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Application No.: US16031988Application Date: 2018-07-10
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Publication No.: US10361710B2Publication Date: 2019-07-23
- Inventor: Yu Lin , Marcello Ganzerli
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Agent Rajeev Madnawat
- Priority: EP17206786 20171212
- Main IPC: H03M1/12
- IPC: H03M1/12 ; H03M1/00 ; H04B1/3805 ; H03M1/16 ; H04B1/401 ; H03M1/18

Abstract:
The present application relates to a reconfigurable analog front-end circuit and a reconfigurable Ethernet transceiver with a reconfigurable analog front-end circuit. The circuit is reconfigurable using the at least one signal-path switching element controlled by a mode signal to operationally establish a first or a second signal path. The first signal path comprises an optional first signal-conditioning section and a shared ADC. The second signal path comprises an optional second signal-conditioning section, an upstream ADC and the shared ADC. The signal paths are selectively switched in response to a mode signal.
Public/Granted literature
- US20190181872A1 RECONFIGURABLE ETHERNET RECEIVER AND AN ANALOG FRONT-END CIRCUIT THEREOF Public/Granted day:2019-06-13
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