公开(公告)号：US09467312B2

公开(公告)日：2016-10-11

申请号：US14202751

申请日：2014-03-10

Applicant: NXP B.V.

Inventor： Marcello Ganzerli ,  Gerrit Willem den Besten

IPC: H04L27/01 ,  H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03146 ,  H04L2025/03484 ,  H04L2025/0349

Abstract: Circuits, apparatus, and methods are disclosed for decision feedback equalization. In one embodiment, an apparatus includes a plurality of time-interleaved slices for processing an input data stream. Each of the slices includes a sampler circuit, a multiplexer, and a latch. In each slice, the multiplexer and the sampler circuit provide sampled output data corresponding to one of a plurality of different versions of the input data stream at times designated uniquely for the slice, according to one or more selection signals. The selection signals are derived from a output of the multiplexer of at least one other of the time-interleaved slices. The latch provides a controlled output in response to the multiplexer and the sampler circuit, as a function of the designated unique times.

Abstract translation: 公开了用于判决反馈均衡的电路，装置和方法。 在一个实施例中，一种装置包括用于处理输入数据流的多个时间交错切片。 每个片包括采样器电路，多路复用器和锁存器。 在每个切片中，多路复用器和采样器电路根据一个或多个选择信号提供对应于输入数据流的多个不同版本中的一个的采样输出数据，该时间是为片唯一地指定的。 选择信号从至少另一个时间交错切片的多路复用器的输出导出。 锁存器响应于多路复用器和采样器电路提供受控输出，作为指定的唯一时间的函数。

公开(公告)号：US11228478B1

公开(公告)日：2022-01-18

申请号：US17069669

申请日：2020-10-13

Applicant: NXP B.V.

Inventor： Marios Neofytou ,  Konstantinos Doris ,  Marcello Ganzerli ,  Georgi Ivanov Radulov ,  Pavlos Athanasiadis

IPC: H04L5/04 ,  H04L27/36 ,  H04L27/12 ,  H04L5/02 ,  H04L27/26 ,  H04L27/00

Abstract: A wireless transceiver system includes a transmitter and a receiver. The transmitter includes a digital processor and a self-correction modulator coupled to the digital processor, wherein based upon a calibration correction assessment of an in-phase (I) signal and a quadrature (Q) signal received from the digital processor, the self-correction modulator generates a calibrated modulated signal. The self-correction modulator includes a core modulator and a calibration correction unit. The calibration correction unit is configured to correct an output of the core modulator based upon the calibration correction assessment. The calibration correction unit includes a calibration processing unit and a calibration modulator, wherein the calibration processing unit provides correction quantities that are used to program the calibration modulator to provide the self-corrected modulated signal.

公开(公告)号：US10983193B2

公开(公告)日：2021-04-20

申请号：US16174997

申请日：2018-10-30

Applicant: NXP B.V.

Inventor： Yu Lin ,  Marcello Ganzerli ,  Mingda Huang

IPC: G01S7/03 ,  G01S13/931 ,  H01Q1/32 ,  H01Q3/26 ,  G01S13/34 ,  G01S13/87 ,  G01S13/86 ,  G01S7/40 ,  G01S13/00 ,  G01S13/02 ,  G01S13/46

Abstract: A communication unit, such as a radar unit (500) includes a plurality of cascaded millimetre wave, mmW, transceiver, TRx, circuit, each comprising at least one phase shift circuit (616) and each coupled to respective antennas; and a signal processor circuit (552) operably coupled to the plurality of cascaded mmW TRx circuits and configured to process transmit and receive signals of the plurality of cascaded mmW TRx circuits. The radar unit (500) further comprises: a first TRx circuit (320) of the plurality of cascaded mmW TRx circuits being configured to wirelessly transmit (360) a signal to a second TRx circuit (322) via a respective antenna; a localization processing circuit (580) operably coupled to at least one of the first TRx circuit (320) and second TRx circuit (322) and configured to wirelessly determine a distance relationship (350) between at least one antenna coupled to the first TRx circuit (320) and at least one antenna coupled to the second TRx circuit (322); and a phase control unit (602), operably coupled to the localization processing circuit (570) and configured to adjust at least one phase shifter (616) in response to the wirelessly determined distance relationship.

公开(公告)号：US10361710B2

公开(公告)日：2019-07-23

申请号：US16031988

申请日：2018-07-10

Applicant: NXP B.V.

Inventor： Yu Lin ,  Marcello Ganzerli

IPC: H03M1/12 ,  H03M1/00 ,  H04B1/3805 ,  H03M1/16 ,  H04B1/401 ,  H03M1/18

Abstract: The present application relates to a reconfigurable analog front-end circuit and a reconfigurable Ethernet transceiver with a reconfigurable analog front-end circuit. The circuit is reconfigurable using the at least one signal-path switching element controlled by a mode signal to operationally establish a first or a second signal path. The first signal path comprises an optional first signal-conditioning section and a shared ADC. The second signal path comprises an optional second signal-conditioning section, an upstream ADC and the shared ADC. The signal paths are selectively switched in response to a mode signal.

公开(公告)号：US20190178983A1

公开(公告)日：2019-06-13

申请号：US16174997

申请日：2018-10-30

Applicant: NXP B.V.

Inventor： YU LIN ,  Marcello Ganzerli ,  Mingda Huang

IPC: G01S7/03 ,  G01S13/93 ,  H01Q3/26 ,  H01Q1/32

Abstract: A communication unit, such as a radar unit (500) includes a plurality of cascaded millimetre wave, mmW, transceiver, TRx, circuit, each comprising at least one phase shift circuit (616) and each coupled to respective antennas; and a signal processor circuit (552) operably coupled to the plurality of cascaded mmW TRx circuits and configured to process transmit and receive signals of the plurality of cascaded mmW TRx circuits. The radar unit (500) further comprises: a first TRx circuit (320) of the plurality of cascaded mmW TRx circuits being configured to wirelessly transmit (360) a signal to a second TRx circuit (322) via a respective antenna; a localization processing circuit (580) operably coupled to at least one of the first TRx circuit (320) and second TRx circuit (322) and configured to wirelessly determine a distance relationship (350) between at least one antenna coupled to the first TRx circuit (320) and at least one antenna coupled to the second TRx circuit (322); and a phase control unit (602), operably coupled to the localization processing circuit (570) and configured to adjust at least one phase shifter (616) in response to the wirelessly determined distance relationship.

公开(公告)号：US11658677B2

公开(公告)日：2023-05-23

申请号：US17490415

申请日：2021-09-30

Applicant: NXP B.V.

Inventor： Lucien Johannes Breems ,  Marcello Ganzerli ,  Chenming Zhang ,  Pierluigi Cenci

IPC: H03M3/00 ,  H03M1/06 ,  H03M1/08

CPC classification number: H03M3/34 ,  H03M1/0626 ,  H03M1/0854 ,  H03M3/32 ,  H03M3/364 ,  H03M3/38

Abstract: A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

公开(公告)号：US20230102232A1

公开(公告)日：2023-03-30

申请号：US17490415

申请日：2021-09-30

Applicant: NXP B.V.

Inventor： Lucien Johannes Breems ,  Marcello Ganzerli ,  Chenming Zhang ,  Pierluigi Cenci

IPC: H03M3/00 ,  H03M1/08 ,  H03M1/06

Abstract: A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

公开(公告)号：US11606102B2

公开(公告)日：2023-03-14

申请号：US17449030

申请日：2021-09-27

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Marcello Ganzerli ,  Pierluigi Cenci ,  Lucien Johannes Breems

IPC: H03M3/00

Abstract: A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency (fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

公开(公告)号：US20220416809A1

公开(公告)日：2022-12-29

申请号：US17449030

申请日：2021-09-27

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Marcello Ganzerli ,  Pierluigi Cenci ,  Lucien Johannes Breems

IPC: H03M3/00

Abstract: A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency(fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

公开(公告)号：US20150256362A1

公开(公告)日：2015-09-10

申请号：US14202751

申请日：2014-03-10

Applicant: NXP B.V.

Inventor： Marcello Ganzerli ,  Gerrit Willem den Besten

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03146 ,  H04L2025/03484 ,  H04L2025/0349

Abstract: Circuits, apparatus, and methods are disclosed for decision feedback equalization. In one embodiment, an apparatus includes a plurality of time-interleaved slices for processing an input data stream. Each of the slices includes a sampler circuit, a multiplexer, and a latch. In each slice, the multiplexer and the sampler circuit provide sampled output data corresponding to one of a plurality of different versions of the input data stream at times designated uniquely for the slice, according to one or more selection signals. The selection signals are derived from a output of the multiplexer of at least one other of the time-interleaved slices. The latch provides a controlled output in response to the multiplexer and the sampler circuit, as a function of the designated unique times.

Abstract translation: 公开了用于判决反馈均衡的电路，装置和方法。 在一个实施例中，一种装置包括用于处理输入数据流的多个时间交错切片。 每个片包括采样器电路，多路复用器和锁存器。 在每个切片中，多路复用器和采样器电路根据一个或多个选择信号提供对应于输入数据流的多个不同版本中的一个的采样输出数据，该时间是为片唯一地指定的。 选择信号从至少另一个时间交错切片的多路复用器的输出导出。 锁存器响应于多路复用器和采样器电路提供受控输出，作为指定的唯一时间的函数。