Invention Grant
- Patent Title: Asymmetric high-k dielectric for reducing gate induced drain leakage
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Application No.: US15813314Application Date: 2017-11-15
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Publication No.: US10374048B2Publication Date: 2019-08-06
- Inventor: Anthony I. Chou , Arvind Kumar , Chung-Hsun Lin , Shreesh Narasimha , Claude Ortolland , Jonathan T. Shaw
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran Cole & Calderon P.C.
- Agent Alvin Borromeo; Andrew M. Calderon
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/51 ; H01L21/265 ; H01L29/66 ; H01L21/28 ; H01L21/02 ; H01L21/426 ; H01L21/8234 ; H01L21/3115 ; H01L21/324 ; H01L29/40 ; H01L21/84 ; H01L29/78 ; H01L21/283 ; H01L21/3065 ; H01L21/308 ; H01L29/417

Abstract:
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
Public/Granted literature
- US20180076039A1 ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE Public/Granted day:2018-03-15
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