Invention Grant
- Patent Title: PNP-type bipolar transistor manufacturing method
-
Application No.: US15911709Application Date: 2018-03-05
-
Publication No.: US10381269B2Publication Date: 2019-08-13
- Inventor: Pascal Chevalier , Gregory Avenier
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Crowe & Dunlevy
- Priority: FR1657067 20160722
- Main IPC: H01L27/102
- IPC: H01L27/102 ; H01L21/8228 ; H01L29/423 ; H01L29/66 ; H01L29/732 ; H01L27/06 ; H01L29/06 ; H01L29/08 ; H01L21/02 ; H01L21/265 ; H01L21/285 ; H01L21/311 ; H01L21/761 ; H01L21/8249 ; H01L27/082

Abstract:
A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.
Public/Granted literature
- US20180197781A1 PNP-TYPE BIPOLAR TRANSISTOR MANUFACTURING METHOD Public/Granted day:2018-07-12
Information query
IPC分类: