Invention Grant
- Patent Title: On-chip reliability monitor and method
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Application No.: US15903231Application Date: 2018-02-23
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Publication No.: US10429434B2Publication Date: 2019-10-01
- Inventor: John A. Fifield , Eric Hunt-Schroeder , Mark D. Jacunski
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Gibb & Riley, LLC
- Agent Michael J. LeStrange, Esq.
- Main IPC: G01R31/26
- IPC: G01R31/26 ; G01R31/28

Abstract:
Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.
Public/Granted literature
- US20190265293A1 ON-CHIP RELIABILITY MONITOR AND METHOD Public/Granted day:2019-08-29
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