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公开(公告)号：US10429434B2
公开(公告)日：2019-10-01
申请号：US15903231
申请日：2018-02-23
Applicant: GLOBALFOUNDRIES INC.
Inventor： John A. Fifield , Eric Hunt-Schroeder , Mark D. Jacunski
Abstract: Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.
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公开(公告)号：US20190265293A1
公开(公告)日：2019-08-29
申请号：US15903231
申请日：2018-02-23
Applicant: GLOBALFOUNDRIES INC.
Inventor： John A. Fifield , Eric Hunt-Schroeder , Mark D. Jacunski
Abstract: Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.
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公开(公告)号：US10535379B2
公开(公告)日：2020-01-14
申请号：US15695457
申请日：2017-09-05
Applicant: GLOBALFOUNDRIES INC.
Inventor： Darren L. Anand , John A. Fifield , Eric D. Hunt-Schroeder , Mark D. Jacunski
Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.
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公开(公告)号：US10020047B2
公开(公告)日：2018-07-10
申请号：US15076139
申请日：2016-03-21
Applicant: GLOBALFOUNDRIES INC.
Inventor： Eric D. Hunt-Schroeder , John A. Fifield , Mark D. Jacunski
IPC: G11C11/00 , G11C11/419 , G11C5/14 , G11C7/12 , G11C11/417
CPC classification number: G11C11/419 , G11C5/145 , G11C7/12 , G11C11/417
Abstract: Approaches for a write assist circuit are provided. The write assist circuit includes a boost capacitor with a first node coupled to a bitline through control logic and a second node connected to a field effect transistor (FET) diode stack, a plurality of boot enabled transistors which each contain a gate connected to a boost control signal, and a controlled current source coupled between a ground signal and the second node of the boost capacitor. In the write assist circuit, the boost capacitor has a discharge path which is controlled to provide a boost voltage which is invariant to a level of a power supply signal.
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