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    Voltage-aware adaptive static random access memory (SRAM) write assist circuit
    4.
    发明授权
    Voltage-aware adaptive static random access memory (SRAM) write assist circuit 有权
    电压感知自适应静态随机存取存储器（SRAM）写辅助电路

    公开(公告)号：US09508420B1

    公开(公告)日：2016-11-29

    申请号：US15009132

    申请日：2016-01-28

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric D. Hunt-Schroeder ,  John A. Fifield ,  Darren L. Anand ,  Kevin A. Batson

    IPC: G11C5/14 ,  G11C11/419

    CPC classification number: G11C11/419

    Abstract: Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level.

    Abstract translation: 提供写辅助电路的方法。 写辅助电路包括多个二进制加权升压电容器，每个二进制加权升压电容器包含耦合到位线的第一节点和连接到相应升压使能晶体管的第二节点，以及多个升压使能晶体管，每个包含连接到升压器的栅极 用于控制相应的二进制加权升压电容器的控制使能信号。 多个升压启动晶体管中的每一个的升压控制使能信号由基于电源电平的编码值来控制。

    On-chip reliability monitor and method
    5.
    发明授权
    On-chip reliability monitor and method 有权

    公开(公告)号：US10429434B2

    公开(公告)日：2019-10-01

    申请号：US15903231

    申请日：2018-02-23

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： John A. Fifield ,  Eric Hunt-Schroeder ,  Mark D. Jacunski

    IPC: G01R31/26 ,  G01R31/28

    Abstract: Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.

    Operational amplifier with current-controlled up or down hysteresis
    8.
    发明授权
    Operational amplifier with current-controlled up or down hysteresis 有权

    公开(公告)号：US09654086B1

    公开(公告)日：2017-05-16

    申请号：US14992426

    申请日：2016-01-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： John A. Fifield ,  Eric D. Hunt-Schroeder

    IPC: H03K3/02 ,  H03K3/0233 ,  H03K5/24

    CPC classification number: H03K3/02337 ,  H03K3/011 ,  H03K5/2481

    Abstract: Disclosed is an op-amp circuit with current-controlled hysteresis that is insensitive to PVT variations. In the circuit, a digital output signal is output from an output buffer based on the output voltage at an output node of an op-amp. A current source is connected to the input side of the op-amp or one of multiple current sources is selectively connected to the input side and enabled when the digital output signal has a high value to provide falling edge hysteresis. Alternatively, a current source is connected to the reference side of the op-amp or one of multiple current sources is selectively connected to the reference side and enabled when the digital output signal is low to provide rising edge hysteresis. Alternatively, current sources are connected to both the input and reference sides and selectively controlled to provide either falling or rising edge hysteresis.

    Memory array including distributed reference cells for current sensing
    10.
    发明授权
    Memory array including distributed reference cells for current sensing 有权

    公开(公告)号：US10446239B1

    公开(公告)日：2019-10-15

    申请号：US16032100

    申请日：2018-07-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： John A. Fifield ,  Eric Hunt-Schroeder

    IPC: G11C16/06 ,  G11C16/28 ,  G11C16/04 ,  G11C16/14 ,  G11C7/06 ,  G11C11/56 ,  G11C16/24 ,  G11C7/12 ,  G11C7/18 ,  G11C16/08

    Abstract: An array of memory cells in rows and columns with each column having a corresponding reference cell and a corresponding comparator. Each memory cell in a given row and given column is connected to a memory wordline for the row and to a memory bitline for the column. Each reference cell is connected to a reference wordline for the reference cells and to a reference bitline. Each comparator for a column has a current mirror with a reference section connected to the reference bitline for the reference cell for the column and a memory section connected to the memory bitline for the memory cells in the column. Each reference section has a current mirror node and all current mirror nodes in the array are connected to reduce mismatch and improve sensing accuracy. Voltages applied to the memory and reference wordlines are varied to provide accurate single-ended sensing, margin testing, etc.

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