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公开(公告)号：US20190165669A1
公开(公告)日：2019-05-30
申请号：US15822318
申请日：2017-11-27
Applicant: GLOBALFOUNDRIES INC.
Inventor： Eric Hunt-Schroeder , John A. Fifield , Dale E. Pontius
Abstract: Methods produce IC devices that include a multiplexor that is electrically connected to a bandgap reference generator and a charge pump. The multiplexor receives voltage levels of a voltage-boosted clock signal being output by the charge pump to the bandgap reference generator. The multiplexor outputs, to the charge pump, either: a retry signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are below a voltage threshold) or a pump signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are not below the voltage threshold). The pump signal causes the charge pump to output the voltage-boosted clock signal to the bandgap reference generator. The retry signal causes the charge pump to not output the voltage-boosted clock signal to the bandgap reference generator, and instead to precharge the charge pump.
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Patent Agency Ranking
公开(公告)号：US10446239B1
公开(公告)日：2019-10-15
申请号：US16032100
申请日：2018-07-11
Applicant: GLOBALFOUNDRIES INC.
Inventor： John A. Fifield , Eric Hunt-Schroeder
IPC: G11C16/06 , G11C16/28 , G11C16/04 , G11C16/14 , G11C7/06 , G11C11/56 , G11C16/24 , G11C7/12 , G11C7/18 , G11C16/08
Abstract: An array of memory cells in rows and columns with each column having a corresponding reference cell and a corresponding comparator. Each memory cell in a given row and given column is connected to a memory wordline for the row and to a memory bitline for the column. Each reference cell is connected to a reference wordline for the reference cells and to a reference bitline. Each comparator for a column has a current mirror with a reference section connected to the reference bitline for the reference cell for the column and a memory section connected to the memory bitline for the memory cells in the column. Each reference section has a current mirror node and all current mirror nodes in the array are connected to reduce mismatch and improve sensing accuracy. Voltages applied to the memory and reference wordlines are varied to provide accurate single-ended sensing, margin testing, etc.
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公开(公告)号：US20190265293A1
公开(公告)日：2019-08-29
申请号：US15903231
申请日：2018-02-23
Applicant: GLOBALFOUNDRIES INC.
Inventor： John A. Fifield , Eric Hunt-Schroeder , Mark D. Jacunski
Abstract: Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.
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公开(公告)号：US10382049B1
公开(公告)日：2019-08-13
申请号：US16122993
申请日：2018-09-06
Applicant: GLOBALFOUNDRIES INC.
Inventor： Eric Hunt-Schroeder , John A. Fifield
Abstract: Disclosed is a calibration circuit and method. The circuit includes: a DAC that outputs an analog parameter and includes output parameter adjustment circuitry; a comparator that receives a reference parameter and the analog parameter; and a control circuit (with select logic) connected to the comparator and DAC in a feedback loop. During a calibration mode, the magnitude of the analog parameter is adjusted by ½ DAC step in one direction and the feedback loop is used to perform a binary search calibration process. During an operation mode, the magnitude of the analog parameter is adjusted by ½ DAC step in the opposite direction. The select logic selects the DAC step identified by the calibration process or the next higher DAC step as a final DAC step. The control circuit outputs a final DAC code corresponding to the final DAC step and the DAC generates a calibrated parameter based thereon.
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公开(公告)号：US10192590B1
公开(公告)日：2019-01-29
申请号：US15788289
申请日：2017-10-19
Applicant: GLOBALFOUNDRIES INC.
Inventor： John A. Fifield , Eric Hunt-Schroeder
Abstract: Differential voltage generators receive an initial target voltage, and provide the initial target voltage to a first offset element and a second offset element. The first offset element includes first transistors, and the second offset element includes second transistors. Each of the first transistors is capable of changing the initial target voltage by a different incremental amount to change the initial target voltage to an altered target voltage. The second transistors are capable of removing a current generated by the first transistors, thereby causing an opposite current and leaving the initial target voltage unaffected on a second output. Each of the first transistors has a corresponding second transistor that produces the same current. A first output is capable of outputting the altered target voltage, and the second output is capable of outputting the initial target voltage.
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公开(公告)号：US10429434B2
公开(公告)日：2019-10-01
申请号：US15903231
申请日：2018-02-23
Applicant: GLOBALFOUNDRIES INC.
Inventor： John A. Fifield , Eric Hunt-Schroeder , Mark D. Jacunski
Abstract: Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.
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