Invention Grant
- Patent Title: Vertical transistors having improved gate length control using uniformly deposited spacers
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Application No.: US15850585Application Date: 2017-12-21
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Publication No.: US10461172B2Publication Date: 2019-10-29
- Inventor: Christopher J. Waskiewicz , Hemanth Jagannathan , Yann Mignot , Stuart A. Sieg
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/02 ; H01L21/3105 ; H01L29/78 ; H01L21/3213 ; H01L21/28 ; H01L29/40 ; H01L21/311

Abstract:
Embodiments of the invention are directed to a method of forming a semiconductor device by forming a channel fin over a substrate, wherein the channel fin includes a plurality of channel fins, wherein a first spacing is defined between adjacent ones of a first set of the plurality of channel fins, wherein a second spacing is defined between adjacent ones of a second set of the plurality of channel fins, wherein the first spacing is not equal to the second spacing. An initial gate structure is formed over the plurality of channels. Formed along sidewalls of the initial gate structure are spacers that each has a predetermined spacer height, wherein a thickness of each of the spacers is insufficient to allow any one of the spacers to fill the first spacing or the second spacing. Portions of the initial gate structure that are not covered by the spacers are removed.
Public/Granted literature
- US20190198642A1 VERTICAL TRANSISTORS HAVING IMPROVED GATE LENGTH CONTROL USING UNIFORMLY DEPOSITED SPACERS Public/Granted day:2019-06-27
Information query
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