Invention Grant
- Patent Title: Seal-ring structure for stacking integrated circuits
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Application No.: US16216133Application Date: 2018-12-11
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Publication No.: US10475772B2Publication Date: 2019-11-12
- Inventor: Yi-Shin Chu , Kuan-Chieh Huang , Pao-Tung Chen , Shuang-Ji Tsai , Yi-Hao Chen , Feng-Kuei Chang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/311 ; H01L21/768 ; H01L23/31 ; H01L23/48 ; H01L23/522 ; H01L23/528 ; H01L23/58 ; H01L23/00 ; H01L25/00

Abstract:
A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.
Public/Granted literature
- US20190109121A1 SEAL-RING STRUCTURE FOR STACKING INTEGRATED CIRCUITS Public/Granted day:2019-04-11
Information query
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