公开(公告)号：US10777539B2

公开(公告)日：2020-09-15

申请号：US16584689

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L25/065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US10157895B2

公开(公告)日：2018-12-18

申请号：US15954772

申请日：2018-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L25/065 ,  H01L21/311 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/58 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US09972603B2

公开(公告)日：2018-05-15

申请号：US15383419

申请日：2016-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L21/768 ,  H01L23/31 ,  H01L25/065 ,  H01L21/311 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/31111 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2225/06541

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US20200027860A1

公开(公告)日：2020-01-23

申请号：US16584689

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L25/065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US20190109121A1

公开(公告)日：2019-04-11

申请号：US16216133

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L21/311 ,  H01L23/528 ,  H01L23/58

CPC classification number: H01L25/0657 ,  H01L21/31111 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2225/06541

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US20180233490A1

公开(公告)日：2018-08-16

申请号：US15954772

申请日：2018-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L25/065 ,  H01L23/58 ,  H01L21/768 ,  H01L25/00 ,  H01L23/00 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/31111 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2225/06541

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US20170186732A1

公开(公告)日：2017-06-29

申请号：US15383419

申请日：2016-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L21/311 ,  H01L21/768 ,  H01L23/58 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/31111 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2225/06541

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US11624985B2

公开(公告)日：2023-04-11

申请号：US17063386

申请日：2020-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Ching Yu ,  Shih-Che Wang ,  Shu-Hao Chang ,  Yi-Hao Chen ,  Chen-Yen Kao ,  Te-Chih Huang ,  Yuan-Fu Hsu

IPC: H01L21/66 ,  G03F7/20 ,  G01N21/956 ,  H01L21/027 ,  G01N21/89 ,  G06T7/00 ,  G01N21/88

Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.

公开(公告)号：US10795270B2

公开(公告)日：2020-10-06

申请号：US15833640

申请日：2017-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Ching Yu ,  Shih-Che Wang ,  Shu-Hao Chang ,  Yi-Hao Chen ,  Chen-Yen Kao ,  Te-Chih Huang ,  Yuan-Fu Hsu

IPC: H01L21/311 ,  G03F7/20 ,  G01N21/956 ,  H01L21/027 ,  G01N21/89 ,  G06T7/00 ,  H01L21/66 ,  G01N21/88

Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.

公开(公告)号：US10475772B2

公开(公告)日：2019-11-12

申请号：US16216133

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L25/065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.