公开(公告)号：US11282769B2

公开(公告)日：2022-03-22

申请号：US16898647

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen

IPC: H01L29/40 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a standard via disposed on a first side of a substrate. An oversized via is disposed on the first side of the substrate and is laterally separated from the standard via. The oversized via has a larger width than the standard via. An interconnect wire vertically contacting the oversized via. A through-substrate via (TSV) extends from a second side of the substrate, and through the substrate, to physically contact the oversized via or the interconnect wire. The TSV has a minimum width that is smaller than a width of the oversized via.

公开(公告)号：US10475772B2

公开(公告)日：2019-11-12

申请号：US16216133

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L25/065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US20210050303A1

公开(公告)日：2021-02-18

申请号：US16537905

申请日：2019-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chien ,  Chien-Hsien Tseng ,  Dun-Nian Yaung ,  Nai-Wen Cheng ,  Pao-Tung Chen ,  Yi-Shin Chu ,  Yu-Yang Shen

IPC: H01L23/552 ,  H01L23/538 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components. Further, the shield structure substantially covers the second electronic component and/or would substantially cover the first electronic component if the semiconductor packaging device was flipped vertically.

公开(公告)号：US10777539B2

公开(公告)日：2020-09-15

申请号：US16584689

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L25/065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US20240339555A1

公开(公告)日：2024-10-10

申请号：US18745245

申请日：2024-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yin-Kai Liao ,  Jen-Cheng Liu ,  Kuan-Chieh Huang ,  Chih-Ming Hung ,  Yi-Shin Chu ,  Hsiang-Lin Chen ,  Sin-Yi Jiang

IPC: H01L31/18 ,  H01L27/146 ,  H01L31/0288

CPC classification number: H01L31/1804 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/0288

Abstract: A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.

公开(公告)号：US11508817B2

公开(公告)日：2022-11-22

申请号：US17036287

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yin-Kai Liao ,  Sin-Yi Jiang ,  Hsiang-Lin Chen ,  Yi-Shin Chu ,  Po-Chun Liu ,  Kuan-Chieh Huang ,  Jyh-Ming Hung ,  Jen-Cheng Liu

IPC: H01L29/10 ,  H01L29/49 ,  H01L29/167 ,  H01L29/66

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.

公开(公告)号：US20220102410A1

公开(公告)日：2022-03-31

申请号：US17177696

申请日：2021-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Lin Chen ,  Yi-Shin Chu ,  Yin-Kai Liao ,  Sin-Yi Jiang ,  Kuan-Chieh Huang ,  Jhy-Jyi Sze

IPC: H01L27/146 ,  H01L31/105

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

公开(公告)号：US20210391302A1

公开(公告)日：2021-12-16

申请号：US16898613

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen ,  Che-Wei Chen

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

公开(公告)号：US20210391237A1

公开(公告)日：2021-12-16

申请号：US16898647

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a standard via disposed on a first side of a substrate. An oversized via is disposed on the first side of the substrate and is laterally separated from the standard via. The oversized via has a larger width than the standard via. An interconnect wire vertically contacting the oversized via. A through-substrate via (TSV) extends from a second side of the substrate, and through the substrate, to physically contact the oversized via or the interconnect wire. The TSV has a minimum width that is smaller than a width of the oversized via.

公开(公告)号：US11037885B2

公开(公告)日：2021-06-15

申请号：US16537905

申请日：2019-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chien ,  Chien-Hsien Tseng ,  Dun-Nian Yaung ,  Nai-Wen Cheng ,  Pao-Tung Chen ,  Yi-Shin Chu ,  Yu-Yang Shen

IPC: H01L23/552 ,  H01L23/538 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components. Further, the shield structure substantially covers the second electronic component and/or would substantially cover the first electronic component if the semiconductor packaging device was flipped vertically.