Invention Grant
- Patent Title: Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
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Application No.: US15676488Application Date: 2017-08-14
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Publication No.: US10475779B2Publication Date: 2019-11-12
- Inventor: Yaojian Lin , Kang Chen , Seung Wook Yoon
- Applicant: STATS ChipPAC Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Brian M. Kaufman; Robert D. Atkins
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L21/768 ; H01L23/522 ; H01L23/31 ; H01L23/498 ; H01L21/56 ; H01L23/538 ; H01L23/552 ; H01L21/683 ; H01L23/00 ; H01L25/065 ; H01L25/10

Abstract:
A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.
Public/Granted literature
- US20180026023A1 Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP Public/Granted day:2018-01-25
Information query
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