Invention Grant
- Patent Title: Interconnect retimer enhancements
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Application No.: US15039515Application Date: 2013-12-26
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Publication No.: US10534034B2Publication Date: 2020-01-14
- Inventor: Daniel S. Froelich , Debendra Das Sharma
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- International Application: PCT/US2013/077806 WO 20131226
- International Announcement: WO2015/099733 WO 20150702
- Main IPC: G01R31/317
- IPC: G01R31/317 ; H04B3/46 ; G06F11/22 ; G01R31/3177 ; G06F11/36 ; H01L21/66 ; G06F11/00 ; G06F13/16 ; G01R31/28 ; G01R31/327 ; G06F11/07
Abstract:
A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.
Public/Granted literature
- US20160377679A1 INTERCONNECT RETIMER ENHANCEMENTS Public/Granted day:2016-12-29
Information query
